[vc_row][vc_column][vc_tta_tabs style=”modern” active_section=”1″][vc_tta_section title=”Overview” tab_id=”1541971500613-0ec4fc59-2bfc”][vc_column_text]RTL Design course is a 4 months course focused on all the aspects of RTL design with complex hands on project coding.

Participants will be working on few simple projects and a complex project to gain complete expertise on synthesisable RTL development.[/vc_column_text][/vc_tta_section][vc_tta_section title=”Syllabus” tab_id=”1541971500620-de7bef0f-b03a”][vc_toggle title=”Advanced Digital Design”]

[/vc_toggle][vc_toggle title=”Verilog”]

[/vc_toggle][vc_toggle title=”System verilog for design”]

[/vc_toggle][vc_toggle title=”Hands on project : DMA Controller RTL coding”]

[/vc_toggle][vc_toggle title=”Linting”]

[/vc_toggle][/vc_tta_section][vc_tta_section title=”Schedule” tab_id=”1541971524428-6b46e3b3-35fe”][vc_column_text]

Course RTL Design and Integration Training
Duration 4 months
Next Batch Adhoc (based on minimum of 10 students)
Saturday & Sunday(9AM – 1PM India time)
Tools Questasim, Spyglass
Mode of training Online training
Tool Access Tool access for complete course duration
Batch Size 10

[/vc_column_text][/vc_tta_section][vc_tta_section title=”FAQs” tab_id=”1541971537543-694723e5-e96c”][vc_toggle title=”Do you offer support after course completion?”]

[/vc_toggle][vc_toggle title=”What are the Course Prerequisites?”]

[/vc_toggle][vc_toggle title=”What if I miss few sessions during course?”]

[/vc_toggle][vc_toggle title=”Course has started few weeks back, can I still join the course in between?”]

[/vc_toggle][/vc_tta_section][vc_tta_section title=”Fee” tab_id=”1606647971852-2f1d76cf-1728″][vc_column_text]


Course Registration