[vc_row][vc_column][vc_tta_tabs style=”modern” active_section=”1″][vc_tta_section title=”Overview” tab_id=”1541971500613-0ec4fc59-2bfc”][vc_column_text]RTL Design course is a 4 months course focused on all the aspects of RTL design with complex hands on project coding.

Participants will be working on few simple projects and a complex project to gain complete expertise on synthesisable RTL development.[/vc_column_text][/vc_tta_section][vc_tta_section title=”Syllabus” tab_id=”1541971500620-de7bef0f-b03a”][vc_toggle title=”Advanced Digital Design”]

• Digital Design basics
• Combinational logic
• Sequential logic, FF, latch, counters
• Memories
• Setup time, Hold time, timing closure, fixing setup time and hold time violations
• STA basic concepts time, Hold time, timing closure, fixing setup time and hold time violations
• www.vlsiguru.com/digital-design-complete

[/vc_toggle][vc_toggle title=”Verilog”]

• Overview of Verilog-2012 synthesizable constructs
• Multiple hands on projects
  • Synchronous and Asynchronous FIFO
  • Interrupt controller
  • SPI Controller
  • Watchdog timer
  • PISO and SIPO
  • I2C controller

[/vc_toggle][vc_toggle title=”System verilog for design”]

• Synthesizable SV constructs

[/vc_toggle][vc_toggle title=”Hands on project : DMA Controller RTL coding”]

• Multi core, Multi channel DMA controller
• Architecture
• Interface definition
• Register definition
• Sub block architecture
• Sub block implementation
  • Verilog TB for standalone verification
• Design integration
  • Verilog TB for complete design

[/vc_toggle][vc_toggle title=”Linting”]

• Lint checks for DMA Controller using Spyglass

[/vc_toggle][/vc_tta_section][vc_tta_section title=”Schedule” tab_id=”1541971524428-6b46e3b3-35fe”][vc_column_text]

Course	RTL Design and Integration Training
Duration	4 months
Next Batch	Adhoc (based on minimum of 10 students)
Schedule
	Saturday & Sunday(9AM – 1PM India time)
Tools	Questasim, Spyglass
Mode of training	Online training
Tool Access	Tool access for complete course duration
Batch Size	10

[/vc_column_text][/vc_tta_section][vc_tta_section title=”FAQs” tab_id=”1541971537543-694723e5-e96c”][vc_toggle title=”Do you offer support after course completion?”]

• Yes, Course fee also includes support for doubt clarification sessions even after course completion
• You have option to mail you queries
• Option to meet in person to clarify doubts

[/vc_toggle][vc_toggle title=”What are the Course Prerequisites?”]

• Digital design expertise
• Verilog coding expertise

[/vc_toggle][vc_toggle title=”What if I miss few sessions during course?”]

• Each session of course is recorded, missed session videos will be shared

[/vc_toggle][vc_toggle title=”Course has started few weeks back, can I still join the course in between?”]

• Yes, You will have option to view the recorded videos of course for the sessions missed
• You will have option to repeat the course any time in next 1 year

[/vc_toggle][/vc_tta_section][vc_tta_section title=”Fee” tab_id=”1606647971852-2f1d76cf-1728″][vc_column_text]

• • Fee: INR 20,000 + GST
  • Confirm your course enrolment by making 5,000 INR transfer to below account.
    • Account Details for fee transfer
  • Payment schedule
    • 5000 INR towards course enrolment
    • 15000 + GST(overall) once course commences

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