physical-design-1-1-training - VLSI Guru

physical-design-1-1-training

1-1 training Highlights

75 hours of 1-1 training at student flexible timings
Support with office work debug (for working professionals)
Complete guided project support, and 1 month tool access(24x7) for hands on practice
Course content can be customized(topics added and removed) as per student requirements
Trainer support outside teaching hours.
Regular mock interviews and assessment tests for performance tracking

Course content - Hourly breakup

Digital design (5 hours)

Topic	Duration(Hours)
Number systems, Radix conversion	1
Combinational logic	2
Sequential logic	2
Total	5

Linux commands (4 hours)

Topic	Duration(Hours)
File and directory commands, file permissions, moving between directories	1
Text display commands, root configuration files, environment variables	1
Text processing commands – Sed, AWK, Grep, Pipe, Xargs	1
Process management, working with server	0.5
File compress and extract commands	0.5
Total	4

TCL scripting (6 hours)

Topic	Duration(Hours)
TCL Basic Commands – Operators, Special variables , loops	2
TCL Lists, string and arrays	1
TCL dictionary and example programs	1
TCL procedure and its example programs	1
TCL regular expression and example programs	1

Total	6

CMOS and semiconductor basics (5 hours)

Topic	Duration(Hours)
Introduction to CMOS basics and types of semiconductor	1
MOSFETs classification and operation	1
CMOS operation and Different CMOS circuits	1
CMOS fabrication and Layout	1
Short channel effects in MOSFET	1
Total	5

PD BASICS ( 4 hours)

Topic	Duration(Hours)
ASIC Design flow	1
Physical design flow	1
Fullchip design, block level design and different types of cells	1
STA Basics	1
Total	4

Advance Physical design (51 Hours)

Topic	Duration(Hours)
Initial Setup	4
Floorplan	15
Static Timing Analysis	6
Placement	8
Clock Tree Synthesis	6
Routing	6
Parasitic extraction and Timing ECO	6
Total	53

Initial Setup (4 hours)

Topic	Duration(Hours)
Installation of tools to access design	1
Input files for PD	1.5
PD work environment setup	1.5
Total	4

Floorplan ( 15 hours)

Topic	Duration(Hours)
sanity checks – LAB	1
Creating core and Die area – Theory	1
Creating core and Die area – LAB	1
Understanding ICC2 tool commands – LAB	1
Port Placement – Theory	1
Port Placement – LAB	1
Macro Placement – Theory	1
Macro Placement – LAB	1
Multi voltage design – Theory	1
Multi voltage design – LAB	1
Physical only cell placement – Theory	1
Physical only cell placement – LAB	1
Power planning – Theory	1
Power planning – LAB	1
Total	15

Static Timing Analysis ( 6 hours )

Topic	Duration(Hours)
Loading input files in NDM format and Different types of clock , clock skew and clock uncertainty	1
Setup and Hold Analysis with examples	1.5
Multicycle and false path	1
Modes , corners and scenarios	1
Understanding MCMM file – LAB	1.5
Total	6

Placement ( 8 hours )

Topic	Duration(Hours)
Coarse Placement – Theory	1
Coarse Placement – LAB	2
Detail Placement – Theory	1
Detail Placement – LAB	1
Congestion analysis and Fixing – LAB	1
analysis – LAB	1
Setup analysis after Placement – LAB	1
Total	8

Clock Tree Synthesis ( 6 hours )

Topic	Duration(Hours)
Understanding CTS constrains – Theory	1.5
Developing CTS spec file – Theory	1.5
Running CTS flow – LAB	1
Analyzing CTS results – LAB	2.5
Total	6

Routing ( 6 hours )

Topic	Duration(Hours)
Understanding routing steps	1
Understanding routing constraints	1.5
Timing Analysis After routing – LAB	1.5
Metal level DRC and LVS fixing – LAB	2
Total	6

Parasitic extraction and Timing ECO ( 6 hours )

Topic	Duration(Hours)
Parasitic extraction (SPEF) using STARRC	1
Prime time flow setup	1
Timing Analysis Using Prime time	2
Timing ECO	2
Total	12

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