1-1 training Highlights

Course content - Hourly breakup

Topic Duration(Hours)
Number systems, Radix conversion 2
Combinational logic 3
Sequential logic 3
Total 8
Topic Duration(Hours)
File and directory commands, file permissions, moving between directories 2
Text display commands, root configuration files, environment variables 2
Text processing commands – Sed, AWK, Grep, Pipe, Xargs 2
Process management, working with server 1
File compress and extract commands 1
Total 8
Topic Duration(Hours)
TCL Basic Commands – Operators, Special variables , loops 3
TCL Lists, string and arrays 2
TCL dictionary and example programs 2
TCL procedure and its example programs 2
TCL regular expression and example programs 2

Total 11
Topic Duration(Hours)
Introduction to CMOS basics and types of semiconductor 2
MOSFETs classification and operation 2
CMOS operation and Different CMOS circuits 2
CMOS fabrication and Layout 2
Short channel effects in MOSFET 2
Total 10
ASIC Design flow2
Physical design flow2
Fullchip design, block level design and different types of cells2
STA Basics2
Initial Setup8
Static Timing Analysis12
Clock Tree Synthesis12
Parasitic extraction and Timing ECO12
Installation of tools to access design2
Input files for PD3
PD work environment setup3


sanity checks – LAB2
Creating core and Die area – Theory2
Creating core and Die area – LAB2
Underatanding ICC2 tool commands – LAB3
Port Placement – Theory2
Port Placement – LAB2
Macro Placement – Theory2
Macro Placement – LAB2
Multi voltage design – Theory2
Multi voltage design – LAB3
Physical only cell placement – Theory2
Physical only cell placement – LAB2
Power planning – Theory3
Power planning – LAB3


Loding input files in NDM format and Different types of clock , clock skew and clock uncertainity2
Setup and Hold Analysis with examples3
Multicylce and false path2
Modes , corners and scenarios2
Underatanding MCMM file – LAB3
Coarse Placement – Theory2
Coarse Placement – LAB3
Detail Placement – Theory2
Detail Placement – LAB2
Congestion analysis and Fixing – LAB2
analysis – LAB2
Setup analysis after Placement – LAB2
Understaing CTS constrains – Theory3
Developing CTS spec file – Theory3
Running CTS flow – LAB2
Analysing CTS results – LAB5
Understanding routing steps2
Understaing routing constraints3
Timing Analysis After routing – LAB3
Metal level DRC and LVS fixing – LAB4
Parasitic extraction (SPEF) using STARRC 33
Prime time flow setup2
Timing Analysis Using Prime time4
Timing ECO3

Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.

Course Registration