Synthesis steps:

1.       Demo example:

·         /home/vlsiguru/PHYSICAL_DESIGN/STUDENT_PROJECTS/SYNTHESIS_DEMO/memory_controller

2.       SDC file :
/home/vlsiguru/PHYSICAL_DESIGN/STUDENT_PROJECTS/SYNTHESIS_DEMO/memory_controller/synth/mem_ctrl.sdc

3.       Synthesis Script

·         /home/vlsiguru/PHYSICAL_DESIGN/STUDENT_PROJECTS/SYNTHESIS_DEMO/memory_controller/dc_script.tcl

4.       Synthesized netlist

·         /home/vlsiguru/PHYSICAL_DESIGN/STUDENT_PROJECTS/SYNTHESIS_DEMO/memory_controller/synth/mem_ctrl_gate.v

Project overview:

·         RTL Code paths

o   /home/vlsiguru/PHYSICAL_DESIGN/STUDENT_PROJECTS/RTL

·         Students are supposed to refer to previous project and design specifications to implement the complete PnR flow

o   Develop SDC file

o   Synthesize the RTL in to netlist : This step is important since the way you synthesize will impact the number of macros in the netlist.

o   Implement complete Physical Design flow for above netlist starting from data preparation to STA closure.

·         Students can choose any of the above projects

·         Students should talk to their trainers to get support for SDC files and synthesis.

·         Final implementation will be reviewed by the respective trainer.