[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_column_text]DIGITAL DESIGN & APTITUDE QUESTIONS(1 TO 35)

Aptitude Questions:
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1. Two pipes A and B can fill a tank in 1 hour 12 minutes and 1 hour 30 minutes, respectively. Pipe C can empty the tank in 1 hour. Intially, Pipes A and B are opened and after 14 minutes C is also opened. In how much time will the tank be full? (L-2)
a. 1 hour b. 80 min. c. 84 min. d. 1 hr 32 min.

2. Two pipes X and Y can fill a cistern in 15 min. and 40 min. respectively. Both pipes are opened together but after 4 minutes, pipe X is turned off. What is the total time required to fill the cistern?
a. 10 min 10 sec b. 25 min 20 sec c. 14 min 40 sec d. 20 min 10 sec

3. Gold is 19 times as heavy as water and copper is 9 times heavy. In what ratio must these metals be mixed so that the mixture may be 15 times as heavy as water?
(A) 4:1 (B) 3:2 (C) 2:1 (D) 1:3

4. A trader has 100 kg of rice, a part of which he sells at 30% profit and the rest at 5% profit. He gains 25% on the whole. What is the quantity sold at 30% gain?
(A) 80 kg (B) 40 kg (C) 75 kg (D) 35 kg

5. 729 ml of a mixture contains milk and water in ratio 7:2. How much of the water is to be
added to get a new mixture containing half milk and half water?

(A) 79 ml (B) 81 ml (C) 72 ml (D) 91 ml

6. The sides of a triangle are in the ratio (1/2):(1/3):(1/4) and its perimeter is 104 cm. The length of the longest side is:
(A) 48 (B) 52 (C) 32 (D) 36

7. Saif purchased 20 dozens of toys at the rate of Rs.375 per dozen. He sold each one at the rate of Rs.33. What was his percentage profit ?
(A) 3.5% (B) 5% (C) 5.6% (D) 6.5%

8. If the income of Ram is more than that of Shyam by 37.5%, then by how much % Shyam’s income is less than that of Ram?
(A) 27% (B) 25% (C) No change (D) None of these

9. A sells an article which costs him Rs.500 to B at a profit of 20%. B then sells it to C, making a profit of 10% on the price he paid to A. How much does C pay B ?
(A) Rs.472 (B) Rs.476 (C) Rs.528 (D) Rs.660

10. Fresh fruit contains 68% water and dry fruit contains 20% water. How much dry
fruit can be obtained from 100 kg of fresh fruits?

(A) 32 kg (B) 40 kg (C) 52 kg (D) 80 kg

11. The average salary of 3 workers is Rs. 95 per week. If one earns Rs.115 and second earns
Rs.65, how much is the salary of the 3rd worker?

(A) Rs.120 (B) Rs. 100 (C) Rs. 105 (D) None of these

12. Some students can complete an assignment in 12 days. How many days will be taken by two times the number of such students for 1/3rd of this assignment?
a. 6 days b. 4 days c. 2 days d. 3 days

13. Rahul can row a certain distance downstream in 6 hour and return the same distance in 9 hour. If the speed of Rahul in still water is 12 km/hr, Find the speed of the stream.
a. 2 kmph b. 2.4 kmph c. 3 kmph d. 1.5 kmph

14. Sachin can cover a distance in 1hr 24min by covering 2/3 of the distance at 4 kmph
and the rest at 5kmph. Then the total distance is?
a. 5 km b. 6 km c. 7 km d. 8 km

15. The remainder when 1!+2!+3!…+50! divided by 5! will be

(A) 21 (B) 14 (C) 9 (D) 33

Digital Electronics Questions:
16.The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.

A. True

B. False

17.What is the difference between a ring shift counter and a Johnson shift counter?

A. There is no difference.

B. A ring is faster.

C. The feedback is reversed.

D. The Johnson is faster.

18.The octal numbering system:

B. groups binary numbers in groups of 4

C. saves time

D. simplifies tasks and saves time

19.The terminal count of a typical modulus-10 binary counter is 1010.

A. True

B. False

20.A serial in/serial out shift register transfers data from one line of a parallel bus to another line one bit at a time.

A. True

B. False

21.Which is not a real advantage of HDL?

A. Using higher levels of abstraction

B. Tailoring components to exactly fit the needs of the project

C. The use of graphical tools

D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project

22.A J-K flip-flop is in a “no change” condition when ________.

A. J = 1, K = 1

B. J = 1, K = 0

C. J = 0, K = 1

D. J = 0, K = 0

23.CMOS is a more dominant IC technology than TTL.

A. True

B. False

24.The field programmable logic array was the first ________ programmable logic device.

A. understandable

B. logic array

C. multifunction

D. nonmemory

25.
Information stored in an EPROM can be erased by prolonged exposure to ultraviolet light.

A. True

B. False

26.When comparing the conversions from digital-to-analog and analog-to-digital, the A/D conversion is generally:

A. less complicated but more time consuming than the D/A conversion.

B. more complicated and more time consuming than the D/A conversion.

C. less complicated and less time consuming than the D/A conversion.

D. more complicated but less time consuming than the D/A conversion.

A. It is slower than the ripple-carry adder.

B. It is easier to implement logically than a full adder.

C. It is faster than a ripple-carry adder.

28.What is the Boolean expression for a four-input OR gate?

A. Y = A + B + C + D

B. Y = A• B • C • D

C. Y = A – B – C – D

D. Y = A \$ B \$ C \$ D

29.The output of a NOT gate is HIGH when ________.

A. the input is LOW

B. the input is HIGH

C. power is applied to the gate’s IC

D. power is removed from the gate’s IC

30.Applying DeMorgan’s theorem to the expression , we get ________.

A.

B.

C.

D.

31.A standard logic device can be connected on a bus system as an open-collector logic device by connecting each output to a ________.

A. discrete transistor

B. 10 k series resistor

C. light-emitting diode

D. CMOS buffer

32.An AND gate is a universal gate.

A. True

B. False

33.In the FLEX10K device, the LE can produce two outputs to drive local (LAB) and global (fast track) interconnects on the chip.

A. True

B. False

34.A PAL uses a programmable OR array followed by a fixed AND array.

A. True

B. False

35.In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?

A. On

B. Off

C. Hi-Z

D. 1011

PHYSICAL DESIGN QUESTIONS (36 TO 70)
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36. What is Clock gating technique
39. If Clock spec file is not provided by top level, then can u do it by urself ?
40. What is preferred and non-prefered Routing layer..?
41. What is Placer max rule
43. How Bound is used to fix the violations
44. What is Partial blockage
45. In which input file, cell delay information will be there?
46. What is Clock – SPEC File
47. Difference between clock buffers and normal buffers
48. What is Target skew ?
49. What is the Goal of CTS
50. How to fix Setup violation
51. How to fix Hold violation
52. What is VT Swapping
53. What is NDR rule?
54. What is difference between SOFT and HARD MACRO.?
55. What is IR-drop
56. What is channel length
57. What will happen if you apply HARD Blockage around macros.?
58. In which case D-CAP cell is used
59. What is local skew and global skew
60. What is the physical difference between clock routing and signal routing..?
61. How do you fix transition violation?
62. Write short notes on LVS
63. Write short notes on FV
64. In which scenario, Setup and hold violations will occur together
65. Why clock buffers are used instead of normal buffers in clock path
66. Why insertion delay should be less
67. Why END-CAP cells are used for each block and not for full chip?
68. How to place macros when the no.of macros are around 500
69. What is channel spacing?
70. Why can’t we do CTS before placement stage[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row]