[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_column_text]Aptitude Questions:
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1. The sum of two numbers is 15 and their geometric mean is 20% lower than their arithmetic mean. Find the numbers.
(a) 11, 4 (b) 12, 3 (c) 13, 2 (d) 10, 5

2. Find the units digit of the expression 256251 + 36528 + 7354.
(a) 4 (b) 0 (c) 6 (d) 5

3. In how many ways can the letters of English alphabet can be arranged so that there are seven letters between the letter A and B?

(A) 24C7 (B) 2!×24P7 (C) 24P7 (D) None of these

4. A bag contains 12 white and 18 black balls. Two balls are drawn in succession without replacement. What is the probability that first is white and second is black?

(A) 18/145 (B) 18/29 (C) 36/135 (D) 36/14

5. Working independently, Tina can do a certain job in 12 hours. Working independently, Ann can do the same job in 9 hours. If Tina works independently at the job for 8 hours and then Ann works independently, how many hours will it take Ann to complete the remainder of the jobs?

(A) 2/3 (B) 3/4 (C) 1 (D) 3

6.A and B can together complete a piece of work in 12 days. A alone can complete in 20 days. If B does the work only for half a day daily, then in how many days A and B together will finish the job?

(A) 10 (B) 11 (C) 20 (D) 15

7. Gold is 19 times as heavy as water and copper is 9 times heavy. In what ratio must these metals be mixed so that the mixture may be 15 times as heavy as water?
(A) 4:1 (B) 3:2 (C) 2:1 (D) 1:3
8. The Value of a machine depreciates 10% annually. If the present value of the machine is Rs 1, 00, 000/- then the total depreciation during 2 years hence will be?
(a)Rs 81, 000 (b) 21, 000 (c) Rs 19, 000 (d) Rs 72, 000

9.If the simple interest is 10.5 % annual and compound interest is 10% annual, find the difference between the interests after 3 years on a sum of 1000?
(a) 15 (b) 12 (c) 16 (d) 11
10. Sumit and Ravi started a business by investing Rs 85000 and 15000 respectively. In what ratio the profit earned after 2 years be divided between Sumit and Ravi respectively?
(A) 17:1 (B) 17:2 (C) 17:3 (D)17:4
11. The ratio of daily wages of two workers is 4:3 and one gets daily Rs. 9 more than the other. What are their daily wages?
(A) Rs. 32 and Rs.24 (B) Rs.60 and Rs. 45 (C) Rs. 80 and Rs. 60 (D) None of these

12. A trader, frauds by 10% while buying and 10% while selling the same. What is the total gain he obtained during the transaction?
(A) 13% (B) 20% (C)10% (D) None of these
13. A sells an article which costs him Rs.500 to B at a profit of 20%. B then sells it to C, making a profit of 10% on the price he paid to A. How much does C pay B ?
(A) Rs.472 (B) Rs.476 (C) Rs.528 (D) Rs.660
14. Saif purchased 20 dozens of toys at the rate of Rs.375 per dozen. He sold each one at the rate of Rs.33. What was his percentage profit ?
(A) 3.5% (B) 5% (C) 5.6% (D) 6.5%
15. The price of an article including the sales tax is Rs 616.The rate of sales tax is 10%, if the shopkeeper has made a profit of 12%, then the cost price of the article is?
(A) 490 (B) 530 (C) 500 (D) 600

Digital Electronics Questions:
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16. Hexadecimal 44 is ________ in binary.

A. 01000100

B. 10011010

C. 01011000

D. 10001100

17. How many inputs of a four-input AND gate must be HIGH in order for the output of the logic gate to go HIGH?

A. any one of the inputs

B. any two of the inputs

C. any three of the inputs

D. all four inputs

18. An invalid digital signal is used as a zero.

A. True

B. False

19. Circuits that exhibit the property of memory normally revert to their original state when the input is removed.

A. True

B. False

20. In VHDL, what is a GENERATE statement?

A. The start statement of a program

B. Not used in VHDL or ADHL

C. A way to get the computer to generate a program from a circuit diagram

D. A way to tell the compiler to replicate several components

21. FLEX10K devices are generally classified as ________.

A. PLDs

B. FPGAs

C. HCPLDs

D. CPLDs

22. Determine tHI and tLO for the circuit given below.

A. tHI = 7.95 s, tLO = 6.24 s

B. tHI = 6.24 s, tLO = 7.95 s

C. tHI = 3.97 s, tLO = 3.21 s

D. tHI = 3.21 s, tLO = 3.97 s

23. The address space of a RAM memory can be expanded using a decoder and additional memory ICs. The output of the decoder should be connected to which input line of the memory?

A. The most significant address inputs

B. The most significant data inputs

C. The read/write line

D. The chip enable

24. Ten TTL loads per TTL driver is known as:

A. noise immunity

B. fan-out

C. power dissipation

D. propagation delay

25. Based on the indications of probe A in the figure given below, what is wrong, if anything, with the circuit?

A. The logic probe is unable to determine the state of the circuit at that point and is blinking to alert the technician to the problem.

B. The output appears to be shorted to Vcc, but is being pulsed by the pulser.

C. The output appears to be LOW, but is being pulsed by the pulser.

D. Nothing appears to be wrong at that point.

26. For the device shown here, assume the D input is LOW, both S inputs are LOW, and the input is LOW. What is the status of the outputs?

A. All are HIGH.

B. All are LOW.

C. All but are LOW.

D. All but are HIGH.

27. The truth table shown below describes the operation of a NOR gate.

A. True

B. False

28. Why is the Schmitt trigger needed in the 60-Hz TTL-level clock pulse generator?

A. to provide a triangle wave

B. to provide a sine wave

C. to provide a rounded pulse waveform

D. to provide a sharp pulse waveform

29. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.

A. opposite, active clock edge

B. inverted, positive clock edge

C. quiescent, negative clock edge

D. reset, synchronous clock edge

30. In a PLD, a blown fuse at an OR gate is a LOW and a blown fuse at an AND gate is a HIGH.

A. True

B. False

31. A major advantage of ECL logic over TTL and CMOS is ________.

A. low power dissipation

B. high speed

C. both low power dissipation and high speed

D. neither low power dissipation nor high speed

32. When a computer is executing a program of instructions, the CPU continually fetches information from those locations in memory that contain (1) the program codes representing the operations to be performed and (2) the data to be operated upon.

A. True

B. False

33. Due to their ability to be easily erased and reused, magnetic memory devices are widely used for RAM.

A. True

B. False

34. Convert the following binary number to octal.
010111100

A. 1728

B. 2728

C. 1748

D. 2748

35. Convert the following binary number to octal.
001101011

A. 1538

B. 3518

C. 2538

D. 3528

PHYSICAL DESIGN QUESTIONS:
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36. Movement of macros depends on horizontal and vertical resources available or required. True or false?
37. Why cell ,pin density are there in design? How you will reduce and explain different techniques?
38. How you will get to know that in particular region, that the cells are having high pins, how you resolve the problem?
39. Difference between CTS Exceptions and Timing Exceptions?
40. What is meant by Multi cycle path? Bydefault if you give inly multicycle path for setup, is there any problem for hold? If problem is there how you will reduce? Explain with waveforms?
41. Clock /2, clock/4 circuits with d flipflops?
42. Design a clock/5 circuit usig T flipflops?
43. Why you done CTS separately ?why you can’t do along with in the placement stage
44. why u applied NDR in CTS , What are the exception you see in CTS .tcl file?
45. Types of buffers and inverter used in clock tree building? And difference between normal buffers and these buffers?
46. What do you meant by scan chain reorder , what is the purpose of it, at which stages it will be done,
47. Timing is good will you leave the problem of max transition? If any problem with it what is the problem created by the max transition violation?
48. U got less setup violation like 1ps what you will do, you won’t bother about it or u will resolve?
49. What is there in UPF and use of it?
50. Techniques u applied to remove congestion in placement stage
51. What is SETUP AND HOLD TIME WITH CIRCUIT AND WAVEFORMS? And draw the waveforms separately when the capture clock is negative edge triggered?
52. What do you mean by Setup Margin ?
53. how do they decide setup time and hold time for particular flop?
54. Propagation delay for a cell, and all the other delay definitions?
55. What is meant by Cell delay ? What will happen if load is increasing to the output pin of cell?
56. Setup and hold slack calculation and explain the resolving techniques if they violated?
57. CRPR mechanism in the tool how it will calculate ?
58. What is meant by pulse width and difference between normal pulse width and min pulse width?
59. Min width, max transition, setup, hold in which priority you will resolve these issues ( give 1 to 4 Preference)?
60. What is the info in every input files like in .V , .TF, .lef, fp.def, .lib, etc?
61. In which format GDSII file will present?
62. Why cross talk will come and techniques to reduce?
63. What is ESD and EM and techniques to resolve it?
64. What is meant by DRC and lvs rules ?
65. How uncertainty value will change from starting stage to ending stage… whether it increase or decrease?
66. What is meant by ECO and what you will do there?
67. How shorts and opens formed and how to resolve?
68. For asynchronous circuit how you perform timing ?
69. Define Truth Table, Excitation Table and Characteristic Tables for All flipflpos?
70. What is meant by Preferred and non Preferred routing?
71. What is meant by Multi source CTS?[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row]