[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_column_text]PHYSICAL DESIGN QUESTIONS (1 to 35)
1. Command to create rectangle core area in the design and command for creating rectilinear block?
2. Difference between Single Voltage Design and Multi Voltage Design?
3. Why PMOS called as pull up and NMOS called as pull down?
4. Why unequal rise and fall times in normal buff/inv and Equal rise and fall times in clk buff/inv?
5. What is meant by crow bar current ?
6. How level shifters will help in power reduction ?
7. What are the low power design techniques ?
8. What is meant by Clock gating and which power is reduced by this technique ?
9. What is meant by Clock gating and which power is reduced by this technique ?
10. Why electron mobility is more than hole mobility?
11. Different regions in cmos characteristics and drain current equations in all regions?
12. What are the initial sanity checks in the design before going to floorplan?
13. What are the constraints present in .SDC?
14. What is meant by .Tf file and what is presented in that?
15. What is meant by Path Grouping? What will happened if we keep extra weight on that groups?
16. What is meant by Macro Modelling?
17. What u will do if you have very less amount of Timing Violation (Let say 1ps)?
18. Let say u met your timing? And there are some logical drc violations. What u will do?
19. What are OCV’s in chip designing? How u will reduce this effect?
20. What are different types of DRC’S with some Examples?
21. If we increase the fanout of a cell, how it will effects the cell delay?
22. Difference between WLDM and NLDM?
23. What is meant by Body Effect ? and types in body effects?
24. What is meant by Vth?
25. What is meant by Pinch off and Punch Through Voltage?
26. What is mean by propagation delay?
27. What is meant by noise margin?
28. Differnce between CPF and UPF?
29. Difference Between Latch and Flipflop ? with some waveforms explanation
30. All basic flops using NAND logic structure?
31. ALL basic gates like not,or,and,nand,nor,exor,exnor using 2×1 mux ?
32. What is meant by source latency and insertion delay?
33. What are the physical cells u used in design ur design ?which purpose u used them?
34. What are the block details , which is designed by you?
35. Pin info in design like how to change location at which scenario u will change the location of i/o ports.
Aptitude Questions: (Next 15 QNS)
1. If a number is increased by 12% and then decreased by 18%, then find the net % change in the number.
(A) 8.16% decrease (B) 8.42 % increase (C) 8.44% decrease (D) 8.18% increase
2. The value of a machine depreciates at the rate of 20% every year. It was purchased 2 years ago. If its present value is 6400, its purchase price was
(A) Rs.9240 (B) Rs.7920 (C) Rs.6400 (D) Rs.10000
3. In a test minimum passing percentage for girls and boys is 35% and 40% respectively. A boy scored 483 marks and failed by 117 marks. What are the minimum passing marks for girls ?
(A) 425 (B) 525 (C) 500 (D) 450
4. A person incurs 5% loss by selling a bat for Rs 1140. At what price should the watch be sold to earn 5% profit?
(A) 1260 (B) 1255 (C) 1270 (D) 1250
5. A man buys 5 horses and 7 bulls for Rs 1950 he sells the horses at a profit of 10%and bulls at a profit of 16% and on the whole his gain is Rs 237 what price does he pay for a horse?
(A) 230 (B) 250 (C) 300 (D) 225
6. Sumit and Ravi started a business by investing Rs 85000 and 15000 respectively. In what ratio the profit earned after 2 years be divided between Sumit and Ravi respectively?
(A) 17:1 (B) 17:2 (C) 17:3 (D)17:4
7. The Value of a machine depreciates 10% annually. If the present value of the machine is Rs 1, 00, 000/- then the total depreciation during 2 years hence will be?
(a) Rs 81, 000 (b) 21, 000 (c) Rs 19, 000 (d) Rs 72, 000
8. Two pipes A and B can fill a tank in 1 hour 12 minutes and 1 hour 30 minutes, respectively. Pipe C can empty the tank in 1 hour. Intially, Pipes A and B are opened and after 14 minutes C is also opened. In how much time will the tank be full? (L-2)
a.1 hour b. 80 min. c. 84 min. d. 1 hr 32 min
9. The average age of 5 members is 21 years. If the age of the youngest member be 5 years, find the average age of the family at the birth of the youngest member
(A) 20 years (B) 19 years (C)13 years (D) None of these
10. A man can complete 3/8 of a work in 24 days . At this rate, how much more time is required to complete the work?
a. 15 days b. 40 days c. 64 days d. 28 days
11. Mr. X can complete a job in 18 days , Mr.Y in 20 days and Mr. Z in 30 days , Mr. Y and Mr.Z start the work and are forced to leave after 4 days . The time taken to complete the remaining work by Mr.X is
a. 12 days b. 18 days c. 20 days d. 26 days
12. A man and a woman 81 miles apart from each other, start travelling towards each other at the same time. If the man covers 5 miles per hour to the women’s 4 miles per hour, how far will the woman have travelled when they meet?
a. 27 b. 36 c. 45 d. none of these
13. A bus without stopping travels at an average speed of 60 km/hr and with stoppages at an average speed of 40 km/hr. What is the total time taken by the bus for stoppages on a route of length 300km?
a. 3 hr b. 4 hr c. 2.5 hr d. 3.5 hr
14. Three numbers are in the ratio 3 : 4 : 5 and their L.C.M. is 2400. Their H.C.F. is:
(A) 200 (B) 80 (C) 40 (D) 120
15. Find the unit’s digit in (5314)98 + (7454)151?
(A) 0 (B) 2 (C) 1 (D) None of these
Digital Electronics Questions:
16.When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.
A. be invalid
B. not change
C. remain unchanged
17. The term synchronous refers to events that do not occur at the same time.
18.A 22-k resistor and a 0.02- F capacitor are connected in series to a 5-V source. How long will it take the capacitor to charge to 3.4 V?
A. 0.44 ms
B. 0.501 ms
C. 0.66 ms
D. 0.70 ms
What is the difference between a retriggerable one shot and a nonretriggerable one shot?
A. The nonretriggerable can only be triggered once.
B. The retriggerable can be triggered many times.
C. The output pulse can be stretched with a nonretriggerable.
D. The output pulse can be stretched with a retriggerable.
The complex programmable logic device (CPLD) features a(n) ________ type of memory.
D. volitile EPROM
For the given circuit, what memory location is being addressed?
Other ________ are often used to interpret or represent binary quantities for the convenience of the people who work with and use these digital systems.
A. analog systems
B. digital systems
C. number systems
D. binary systems
The binary number 101110101111010 can be written in octal as ________.
Select one of the following statements that best describes the parity method of error detection.
A. Parity checking is best suited for detecting single-bit errors in transmitted codes.
B. Parity checking is not suitable for detecting single-bit errors in transmitted codes.
C. Parity checking is capable of detecting and correcting errors in transmitted codes.
D. Parity checking is best suited for detecting double-bit errors that occur during the transmission of codes from one location to another.
In Boolean algebra, the word “literal” means ________.
A. a product term
B. all the variables in a Boolean expression
C. the inverse function
D. a variable or its complement
26. Write excitation table for D Flip-flop.
The final output of a modulus-8 counter occurs one time for every ________.
A. 8 clock pulses
B. 16 clock pulses
C. 24 clock pulses
D. 32 clock pulses
is in the form of a sum-of-products expression.
The resolution of a DAC can be expressed as the ________.
A. minimum output voltage
B. number of bits that are converted to an analog output
C. deviation of the output from a straight line
D. difference between the expected and actual outputs
A basic multiplexer principle can be demonstrated through the use of a:
A. single-pole relay
B. DPDT switch
C. rotary switch
D. linear stepper
A truth table with output columns numbered 0–15 may be for which type of decoder IC?
A. hexadecimal 1-of-16
B. dual octal outputs
How many buses are connected as part of the 8085A microprocessor?
The output of the circuit in the given figure (a) at point X on figure (b) will be ________.
A. 1.011 V
B. 2.75 V
C. –1.011 V
D. –2.75 V
One advantage TTL has over CMOS is that TTL is ________.
A. less expensive
B. not sensitive to electrostatic discharge
D. more widely available
Show from the truth table how an exclusive-OR gate can be used to invert the data on one input if the other input is a special control function.
A. Using A as the control, when A = 0, X is the same as B. When A = 1, X is the same as B.
B. Using A as the control, when A = 0, X is the same as B. When A = 1, X is the inverse of B.
C. Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the same as B.
D. Using A as the control, when A = 0, X is the inverse of B. When A = 1, X is the inverse of B.[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row]
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