[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_column_text]Questions: 60

Duration: 3 hours

Submit : 13/July/2018

pd questions

1. In a circuit, for reg to reg path …Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
2. what are the clock tree exceptions explain .
3. why setup and hold time is required?
4. write down the Setup slack equation by considering uncertainity, CPPR.
5. write down the hold slack equation by considering uncertanitiy and cppr.
6. how to fix setup and hold violation?
7. what is CPPR/CRPR and why u need to consider?
8. how tool does area recovery ?
9. what are the inputs for placement ?
10. what checks u will do after placement?
11. why after CTS hold fixed is done?
12. What is uncertainty? Why it occurs write down the reason?
13. what is temperature inversion explain with current equation.
14. What is transition? What if transition time is more?

15.How will you decide the die size?

1. If u have 9 metal layer in your design . Which metal layer u will use for power planning and CTS ? EXplain.
2. How to reduce dynamic IR drop and Static IR Drop?
3. What is cell delay and net delay? On which factor it depends?
4. what are the placement blockages. Explain the types of blockages.
5. why jitter is not considered post cts? write down the uncertainty equation pre CTS and Post CTS.
6. what is clock gating ? Explain with diagram.
7. what is power gating ? Explain difference between clock and power gating.
8. What is OCV , POCV and AOCV? Explain.
9. what is ECO? write down the types of ECO.
10. What is Spare cell ? Which stage you will use spare cell?
11. write down the formula to calculate the channel width.

27.One of the naïve approaches to handle the clock skew problem is:

1. Increase the time period of the clock.
2. Balance the delays of the critical paths in the circuit.
3. Equalize the worst-case delays of every combinational block between pairs of register stages.
4. None of the above.

28.Why do we use buffers in a clock tree?

1. To reduce the delay.
2. To reduce the area requirement.
3. To generate multiple phases of a clock.
4. None of the above.

29.The propagation delay of a long interconnection line can be reduced by:

1. Making the line thinner.
2. Making the line wider.
3. Inserting one or more buffers along the line.
4. All of the above
5. Cloning of a gate can reduce the delay when:
6. When the number of fanout connections from the gate is large.
7. All the fanout targets are located close to one another.
8. The input interconnection delay of the gate is large.
9. None of the above.

31.It is sometimes necessary to deliberately add clock skew so that:

The total delay of the combinational sections between sequential storage elements are made equal.

The clock frequency can be increased without moving gates across storage elements.

The power consumption is reduced.

None of the above.

32. Suppose that a long interconnection line is split into four shorter segments by inserting repeaters. Which of the following statement is true?

a. The total delay increases by an amount equal to the delay of three repeaters.

b. The RC delay reduces sqrt(4) = 2 times.

c. The RC delay reduces by 4 times. d. None of the above.

33. what are the delay models. Explain.

34. when clocks nets are routed at which stage ?

35. why delay decreses when upsizing is done?

36. what is latency? Explain the types of latency?

37. Does crosstalk always causes setup and violation?

38. What is EM how to reduce EM ?

39. What is virtual and real clock ? why virtual clock is used?

Tool Questions

1. Explain Set_Driving_cel?
2. Explain Set_max_delay command ?
3. write down the command to generate clock CLK1 of port Q1 of period 10.
4. what command is used to set multicycle and false path?
5. write the command to create core size ?
6. Write the command to set uncertanity .

Digital Questions

46.The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________

1. a) 01110
2. b) 00001
3. c) 00101
4. d) 00110

47.The given hex number (1E.53)16 is equivalent to

a) (35.68)8

b) (35.24)8

c) (34.34)8

d) (35.59)8

48.How many NOT gates are required for the construction of a 4-to-1 multiplexer?

a) 3

b) 4

c) 2

d) 5

50.In a combinational circuit, the output at any time depends only on the _______ at that time.

1. a) Voltage
2. b) Intermediate values
3. c) Input values
4. d) None of the Mentioned

51.Ring shift and Johnson counters are:

1. a) Synchronous counters
2. b) Asynchronous counters
3. c) True binary counters
4. d) Synchronous and true binary counters

52.The addition of +19 and +43 results as _________ in 2’s complement system.

1. a) 11001010
2. b) 101011010
3. c) 00101010
4. d) 00111110

CMOS/VLSI test

53.Difference between short channel mosfet and long channel mosfet.

1. If you interchange the pmos and nmos in CMOS inverter, will it

still work like a inverter…if not then what will be its properties?

55.Why we prefer enhancement mosfet over depletion mosfet?

56.Explain CMOS inverter input output characteristics.

57.If both the transistors are in saturation, then they act as

1. a) current source
2. b) voltage source
3. c) divider
4. d) buffer

58.CMOS inverter has ______ output impedance

1. a) low
2. b) high

59.Mobility depends on

a) transverse electric field

b) Vg

c) Vdd

d) Channel length

60. Why do we prefer NAND over NOR for digital designs?

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