[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_column_text]Total Questions: 60, Total marks : 60

Duration: 3 hours

Submit by: 10PM, 12/July/2018

PD questions

1.Match the following.
A. Partitioning
B. Floorplanning
C. Placement
D. Routing
(i) Takes a set of blocks of defined shapes and pin locations, and assigns the blocks to exact locations on the layout surface.
(ii) Takes the netlists in some particular order, and provides interconnection among them. (iii) Tries to define exact shapes of the blocks to minimize layout area.
(iv) Breaks a netlist into several pieces that can be laid out separately on the layout surface.
a. A-(iv), B-(iii), C-(i), D-(ii)
b. A-(iv), B-(i), C-(iii), D-(ii)
c. A-(iv), B-(ii), C-(i), D-(iii)
d. None of the above
2. What is signal integrity? How it affects Timing?
3. What is IR drop? How to avoid .how it affects timing?
4.What is EM and it effects?
5. What are types of routing?
6.What is local skew and global skew?
7. What is latency? Give the types?
8.What is multicycle path explain with example?
9. what is latch up. Explain with Diagram ? how to avoid latchp?
10. what is antena effect? If you have antena violation in higher metal layer how you will fix?
11. How to calculate core ring and stripe widths?
12. What is threshold voltage? How it affect timing?
13. what is LEF what is the significance of it in PD?
14. What is .lib , SDC file ?What information it contains?
15.What is goal of CTS? what is false path explain with diagram.
16.What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
17.What is setup and hold time of flop? What if setup and hold violates? Can u do tapeout with setup or hold violation? Explain in detail?
18. what are the input of pd ? Explain all inputs and outputs of each stage in detail?
19. Explain pd flow?
20. what is Synthesis? what are the types of synthesis?
21.what is congestion? How to fix it?
22. What is difference between normal buffer and clock buffer?
23.What is cross talk? How can you avoid crosstalk?
24. What is difference between HFN and CTS?
25.For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
26. If the routing congestion exists between two macros, then what will you do?
27.How will you decide the die size?
28. what guidlines u will keep in mind to place macro?
29. How delays vary with different PVT conditions? Show the graph.
30. what are the physical cells? At what stage in pd it is used?
tool related question
31. what command in icc is used to find the total number of clock , macro and standard cell in design ? write all the command.
32. write the command in icc to see setup and hold violation?
33. what commands do u use to do sanity check?
34. when you use route_opt command in icc what tool does intenally mention all steps?
35. what command is used to do placement in icc?

Digital Test

36. what are the minimum number of 2:1 multiplexer required to generate 2 input and gate and 2 input EX-OR gate?
a. 1and 2 b. 1 and 3 c. 1 and 1 d. 2 and 2
37.what is 8:1 multiplexer explain its functionality with diagram ?
38. what is difference between flip flop and latch? which consumes more power?
39. what is master slave flip flop? explain with diagram?
40. The initial contents of 4 bit serial in parallel out shif reg is 0110 . After three pulse what is output?
41. Implement AND, OR, NOT, NAND, NOR, XOR, XNOR using 2:1 MUX.
42.When is a flip-flop said to be transparent?
a) When the Q output is opposite the input
b) When the Q output follows the input
c) When you can see through the IC packaging
d) None of the Mentioned
43.On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
a) The clock pulse is LOW
b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH
d) The clock pulse transitions from HIGH to LOW
44.Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
a) 10.24 kHz
b) 5 kHz
c) 30.24 kHz
d) 15 kHz
45.Which gate can implement both inverter and buffer?
46. Implement AB + CDE using NAND.
47.Implement the expression X= A’B + A’B’C’ using 2:1 MUX.
48. Build a 4×16 decoder using 2×4 decoder.
49.A modulus-10 counter must have ________
a) 10 flip-flops
b) Flip-flops
c) 2 flip-flops
d) Synchronous clocking
50.A shift register is defined as
a) The register capable of shifting an information to another register
b) The register capable of shifting an information either to the right or to the left
c) The register capable of shifting an information to the right only
d) The register capable of shifting an information to the left only

CMOS /VLSI TEST

51. what is FINFET?
52. what is MOSFET? Explain the region of operaton of mosfet?
53. Write down the steps involved in IC manufacturing?
54.In CMOS technology p-well or N-well region can be formed using
a. low pressure chemical vapour deposition
b. low energy sputtering
c. low temperature dry oxidation
d. low energy ion implemention
55. why nand gate is preffered over NOR gate fabrication?
56. what is the fundamental difference between mosfet and bjt?
57.Explain the sizing of inverter?
58. Implement nand gate using CMOS?
59 . Implement AND and OR gate using cmos.
60. what is Body Effect?[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row]

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