[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_column_text]Aptitude Questions:
1. It is often said, “Rome was not built in a day”. But if there are 2000 walls in Rome and each wall has 3000 bricks. It takes 2 seconds for one worker to fix a brick. How much time would have been taken to build Rome if there were 100 such workers?

(A) less than a day (B) 1-2 days (C) 2-3 days (D) 4-5 days

2. 20 labourers can do a work in 20 days, if everybody works for 6 hours daily. Then 25 labourers can do the same work in 12 days by working daily for: [INFOSYS]

(A) 8 hours (B) 6 hours (C) 4 hours (D) 10 hours

3. Yana and Gupta leave points x and y towards y and x respectively simultaneously and travel in the same route. After meeting each other on the way, Yana takes 4 hours to reach her destination, while Gupta takes 9 hours to reach his destination. If the speed of Yana is 48 km/hr, what is the speed of Gupta?
a. 72 kmph b. 32 kmph c. 20 kmph d. None of these

4. The Ghaziabad-Hapur-Meerut EMU and the Meerut-Hapur-Ghaziabad EMU start at the same time from Ghaziabad and Meerut and proceed towards each other at 16 km/hr and 21 km/hr respectively. When they meet, it is found that one train has travelled 60 km more than the other. The distance between two stations is:
a. 445 km b. 444 km c. 440 km d. 450 km

5. Rajesh walks to and fro to a shopping mall. He spends 30 minutes shopping. If he walks at speed of 10 km an hour, he returns to home at 19.00 hours. If he walks at 15 km an hour, he returns to home at 18.30 hours. How fast must he walk in order to return at 18.15 hours?
a. 17 km/hr b. 18 km/hr c. 19 km/hr d. 20 km/hr

6. An urgent message had to be delivered from the house of the Peshwas in Pune to Shivaji who was camping in Bangalore. A horse rider travels on horseback from Pune to Bangalore at a constant speed. If the horse increased its speed by 6 km/ h, it would take the rider 4 hours less to cover that distance. And travelling with a speed 6 km/ h lower than the initial speed, it would take him 10 hours more than the time he would have taken had he travelled at a speed 6 kmph higher than the initial speed. Find the distance between Pune and Bangalore.
(a) 120 km (b) 600 km (c) 720 km (d) 750 km

7. The charges of a hired car are Rs. 7 per km for the first 80 km, Rs. 5 per km for the next 60 km and Rs. 11 for every 5 km for further journey. If the charges for a journey is Rs. 1212, what is the distance travelled in the journey?

(A) 300 km (B) 240 km (C) 360 km (D) 200 km

8. The boy goes to school reaches the railway station at his 1/3 of his journey & a mill at 1/4 of his journey. The time taken for him to walk between the railway station & the mill is 5 mins. Also he reaches the railway station at 7.35am. So when does he start from his house?

(A) 7:20 am (B) 7:15 am (C) 7:05 am (D) None of these

9. Three numbers, which are co-prime to one another are such that the product of the first two is 551 and that of the last two is 1073. The sum of the three numbers is:

(A ) 75 (B) 81 (C) 85 (D) 89

10. A number when successively divided by 5, 3, 2 gives remainder 0, 2, 1 respectively in that order. What will be the remainder when the same number is divided successively by 2, 3, 5 in that order.

(A) 4, 3, 2 (B) 1, 0, 4 (C) 2, 1, 3 (D) 4, 1, 2

11. What is the sum of the numbers between 300 and 400 such that when they are divided by 6, 9 and 12, they leave same remainders 4 in each case.

(A) 482 (B) 692 (C) 512 (D) 342

12. What is the largest integer that divides all three numbers 23400, 272304, 205248 without leaving a remainder?

(A) 48 (B) 24 (C) 96 (D) 72
13. The difference between a two-digit number and the number obtained by interchanging the digits is 36.What is the difference between the sum and the difference of the digits of the number if the ratio between the digits of the number is 1:2?

(A) 4 (B) 8 (C) 16 (D) None of these

14. Six bells commence tolling together and toll at intervals 2, 4, 6, 8, 10 and 12 seconds, respectively. In 30 minutes, how many times they toll together?

(A) 4 (B) 10 (C) 15 (D) 16

15. Find the sum of prime factors of 561.

(A) 31 (B) 12 (C) 40 (D) 41

Digital Electronics Questions:
16.When Karnaugh mapping, we must be sure to use the ________ number of loops.

A. maximum

B. minimum

C. median

D. Karnaugh

For the input values (A0–A3, B0–B3, Data Select = 1) given for the circuit given below, what will be indicated on the displays?

A. A = 0, B = 5

B. A = 5, B = 0

C. A = 6, B = 0

D. A = 0, B = 6

18.ECL IC technology is faster than TTL technology.

A. True

B. False

19.In a digital reproduction of an analog curve, accuracy can be increased by ________.

A. sampling the curve more often

B. sampling the curve less often

C. decreasing the number of bits used to represent each sampled value

D. all of the above

20.X-ray, MRI, and ultrasound systems in hospitals are examples of analog systems.

A. True

B. False

21.In DRAM operations, it is assumed that R/W is in its ________ state during a ________ operation.

A. HIGH, read

B. Hi-Z, write

C. HIGH, write

D. Hi-Z, read

22.One output structure of a TTL gate is often referred to as a ________.

A. totem-pole arrangement

B. diode arrangement

C. JBT arrangement

D. base, emitter, collector arrangement

23.The nominal value of the dc supply voltage for TTL and CMOS is ________.

A. +3 V

B. +5 V

C. +9 V

D. +12 V

24.An eight-line multiplexer must have as inputs ________.

A. four data inputs and three select inputs

B. eight data inputs and two select inputs

C. eight data inputs and three select inputs

D. eight data inputs and four select inputs

25.What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called?

A. tristate

B. end around

C. universal

D. conversion

26.VARIABLES are considered to be updated ________ within a sequence of statements in a PROCESS, whereas SIGNALS referred to in a PROCESS are updated when the PROCESS ________.

A. once, starts

B. immediately, suspends

C. twice, ends

D. never, starts

27. In AHDL macrofunctions, the first thing that should go into any source file is ________ your code.

A. a field of comments that documents

B. a library of

C. a function name of

D. the universal global definition of

28.Which type of gate can be used to add two bits?

A. Ex-OR




29.A logic probe is placed on the output of a gate and the display indicator is dim. A pulser is used on each of the input terminals, but the output indication does not change. What is wrong?

A. The output of the gate appears to be open.

B. The dim indication on the logic probe indicates that the supply voltage is probably low.

C. The dim indication is a result of a bad ground connection on the logic probe.

D. The gate may be a tristate device.

30.Even-parity 01101000 binary is ________in hexadecimal.

A. C816

B. 6816

C. D016

D. Nothing. Parity does not check.

31.When the 2’s-complement system is used, the number to be subtracted is changed to its 2’s complement and then added to the minuend.

A. True

B. False

32.The mask ROM is ________.

A. MOS technology

B. diode technology

C. resistor-diode technology

D. DROM technology

33.The fan-out of CMOS gates is frequency dependent.

A. True

B. False

34.An unused input of a NAND gate can be left unconnected, pulled high by a pull-up resistor and tied together with another input and not change the logic output.

A. True

B. False

35.PRESET and CLEAR inputs are normally synchronous.

A. True

B. False



1) Chip utilization depends on ___.

a. Only on standard cells
b. Standard cells and macros
c. Only on macros
d. Standard cells macros and IO pads

2) In Soft blockages ____ cells are placed.

a. Only sequential cells
b. No cells
c. Only Buffers and Inverters
d. Any cells

3) Why we have to remove scan chains before placement?

a. Because scan chains are group of flip flop
b. It does not have timing critical path
c. It is series of flip flop connected in FIFO
d. None

4) Delay between shortest path and longest path in the clock is called ____.

a. Useful skew
b. Local skew
c. Global skew
d. Slack

5) Cross talk can be avoided by ___.

a. Decreasing the spacing between the metal layers
b. Shielding the nets
c. Using lower metal layers
d. Using long nets

6) Prerouting means routing of _____.

a. Clock nets
b. Signal nets
c. IO nets
d. PG nets

7) Which of the following metal layer has Maximum resistance?

a. Metal1
b. Metal2
c. Metal3
d. Metal4

8) What is the goal of CTS?

a. Minimum IR Drop
b. Minimum EM
c. Minimum Skew
d. Minimum Slack

9) Usually Hold is fixed ___.

a. Before Placement
b. After Placement
c. Before CTS
d. After CTS

10) To achieve better timing ____ cells are placed in the critical path.

a. HVT
b. LVT
c. RVT
d. SVT

11) Leakage power is inversely proportional to ___.

a. Frequency
b. Load Capacitance
c. Supply voltage
d. Threshold Voltage

12) Filler cells are added ___.

a. Before Placement of std cells
b. After Placement of Std Cells
c. Before Floor planning
d. Before Detail Routing

13) Search and Repair is used for ___.

a. Reducing IR Drop
b. Reducing DRC
c. Reducing EM violations
d. None

14) Maximum current density of a metal is available in ___.

a. .lib
b. .v
c. .tf
d. .sdc

15) More IR drop is due to ___.

a. Increase in metal width
b. Increase in metal length
c. Decrease in metal length
d. Lot of metal layers

16) The minimum height and width a cell can occupy in the design is called as ___.

a. Unit Tile cell
b. Multi heighten cell
c. LVT cell
d. HVT cell

17) CRPR stands for ___.

a. Cell Reconvergence Pessimism Removal
b. Cell Reconvergence Preset Removal
c. Clock Reconvergence Pessimism Removal
d. Clock Reconvergence Preset Removal

18) In OCV timing check, for setup time, ___.

a. Max delay is used for launch path and Min delay for capture path
b. Min delay is used for launch path and Max delay for capture path
c. Both Max delay is used for launch and Capture path
d. Both Min delay is used for both Capture and Launch paths

19) “Total metal area and(or) perimeter of conducting layer / gate to gate area” is called ___.

a. Utilization
b. Aspect Ratio
c. OCV
d. Antenna Ratio

20) The Solution for Antenna effect is ___.

a. Diode insertion
b. Shielding
c. Buffer insertion
d. Double spacing

21) To avoid cross talk, the shielded net is usually connected to ___.

a. VDD
b. VSS
c. Both VDD and VSS
d. Clock

22) If the data is faster than the clock in Reg to Reg path ___ violation may come.

a. Setup
b. Hold
c. Both
d. None

23) Hold violations are preferred to fix ___.

a. Before placement
b. After placement
c. Before CTS
d. After CTS

24) Which of the following is not present in SDC ___?

a. Max tran
b. Max cap
c. Max fanout
d. Max current density

25) Timing sanity check means (with respect to PD)___.

a. Checking timing of routed design with out net delays
b. Checking Timing of placed design with net delays
c. Checking Timing of unplaced design without net delays
d. Checking Timing of routed design with net delays

26) Which of the following is having highest priority at final stage (post routed) of the design ___?

a. Setup violation
b. Hold violation
c. Skew
d. None

27) Which of the following is best suited for CTS?

b. BUF
c. INV

28) Max voltage drop will be there at(with out macros) ___.

a. Left and Right sides
b. Bottom and Top sides
c. Middle
d. None

29) Which of the following is preferred while placing macros ___?

a. Macros placed center of the die
b. Macros placed left and right side of die
c. Macros placed bottom and top sides of die
d. Macros placed based on connectivity of the I/O

30) Routing congestion can be avoided by ___.

a. placing cells closer
b. Placing cells at corners
c. Distributing cells
d. None

31) Pitch of the wire is ___.

a. Min width
b. Min spacing
c. Min width – min spacing
d. Min width + min spacing

32) In Physical Design following step is not there ___.

a. Floorplaning
b. Placement
c. Design Synthesis
d. CTS

33) In technology file if 7 metals are there then which metals you will use for power?

a. Metal1 and metal2
b. Metal3 and metal4
c. Metal5 and metal6
d. Metal6 and metal7

34) If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?

a. Metal1 and metal2
b. Metal3 and metal4
c. Metal4 and metal5
d. Metal6 and metal7

35) In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be ___.

a. 1ns
b. 3ns
c. 5ns
d. 6ns

36) Difference between Clock buff/inverters and normal buff/inverters is __.

a. Clock buff/inverters are faster than normal buff/inverters
b. Clock buff/inverters are slower than normal buff/inverters
c. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/inverters
d. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters.

37) Which configuration is more preferred during floorplaning ?

a. Double back with flipped rows
b. Double back with non flipped rows
c. With channel spacing between rows and no double back
d. With channel spacing between rows and double back

38) What is the effect of high drive strength buffer when added in long net ?

a. Delay on the net increases
b. Capacitance on the net increases
c. Delay on the net decreases
d. Resistance on the net increases.

39) Delay of a cell depends on which factors ?

a. Output transition and input load
b. Input transition and Output load
c. Input transition and Output transition
d. Input load and Output Load.

40) After the final routing the violations in the design ___.

a. There can be no setup, no hold violations
b. There can be only setup violation but no hold
c. There can be only hold violation not Setup violation
d. There can be both violations.

41) Utilisation of the chip after placement optimisation will be ___.

a. Constant
b. Decrease
c. Increase
d. None of the above

42) What is routing congestion in the design?

a. Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above

43) What are preroutes in your design?

a. Power routing
b. Signal routing
c. Power and Signal routing
d. None of the above.

44) Clock tree doesn’t contain following cell ___.

a. Clock buffer
b. Clock Inverter
c. AOI cell
d. None of the above

45)The shortcut import_designs includes reading in the timing constraints file.
True / False

46) Clock uncertainty
a. Is used to model clock skew pre-CTS
b. Is used during CTS as the maximum skew constraint
c. Is used to model clock skew post-CTS
d. A and B

47) Area recovery can:
a. Reduce congestion
b. Increase delay
c. Reduce power consumption
d. A and C
e. A, B and C
During Data Setup it is recommended to apply an “ideal network” on high-fanout nets (enable, reset),
and to remove “ideal network” from the clock network.
True or False?

Applying a power or area critical range can help to reduce power consumption or cell area, respectively.
True or False?

What does initialize_floorplan do?

1. Defines placement rows within the core area
2. Defines the chip boundary or periphery area
3. Places IO pad cells in their defined locations
4. Places macro cells per their placement constraints

d)All of the above


A “soft” placement blockage will:
a. Allow only timing-critical cells to be placed
b. Allow only non timing-critical cells to be placed
c. Allow cell placement only during initial coarse placement
d. Prevent cell placement during initial coarse placement

Circle the correct statement(s) about what create_fp_placement does by default:
a. Optimizes logic (cell sizing, buffering) to improve timing
b. Legally places std cells and non-fixed macros to minimize
wire length
c. Optimizes placement to improve timing
d. Clumps cells from the same logical hierarchy together

Comparing “9/1” and “20/12” in a congestion map:
a. They are equally bad
b. 20/12 is worse because both numbers are much larger
c. 9/1 is worse the ratio is much larger
d. Can not tell without also comparing their “heat” colors

Circle the correct statement(s) about PNS:
a. Allows what-if analysis based on different user constraints
b. Creates DRC/ERC clean routes with synthesize_fp_rail
c. Can automatically calculate the width and number of straps
based on power and IR-drop constraints
d. Allows what-if analysis with “virtual” IO signal pads

By default, place_opt will
a. Optimize placement and logic for congestion
b. Optimize placement and logic for setup timing
c. Optimize logic for leakage power
d. A and B
e. A, B and C

1. Write the command to check for any library inconsistencies & dump report in report file with name lib_consistency.rpt.
2. New to copy design database from /home/pd_training/lab1 to users home directory.
3. How to see what are CELs stored in mwdb?
4. Write full command to create core area & die are in aspect ratio 1.0 & utilization70%, I/O clearance is 10 micron each side.
5. Write command to select a port from GUI & find which metal layer used for selected port?
6. (i) Write command to find if ports are fixed from their attribute.
(ii) If not fixed, make all ports as fixed using command.
7. What is the use of cut_row.tcl that is being used before powerplan?
8. Write a command to verify whether power and ground pins of std cells, macros, pad cells are connected to corresponding power & ground nets.
9. Write a command to select all macros cell.
10. Write Command to find if there is un connected PG pins.
11. List all the clocks & period in your design using commands.
12. Write a command to generate the timing report for setup.
13. In placement and CTS stage we haven’t done routing. How does report.timing calculate the timing delays on the nets?
14. Write command to find num of all ports,clocks & macros are used in design.
15. Write final database for PV in Calibre or ICV like netlist, GDSii or Defs.
16. Write separate commands to ………………………………………………………………………………………………………… 6 MARKS
(i) Global Routing
(ii) Track assignments
(iii) Detail routing
17. Write single command to do all three tasks mentioned above.
18. Write a command to find all type of violations.
19. Write a command to dump only hold report.
20. Write a command to check shorts & open in design.
21. How to define new routings rule explicitly .
22. What are sanity checks before floorplanning?
23. What is the significance of set_zero_interconnect_delay_mode true?
24. Command to check quality of your placement.
25. Write command to general congestion report.

26. Write Linux commands to perform following operations.
1.Make a directory ZIYA
2.Make files x1, x2, and x3.
3.Make a text file x4 and write “I love my India”.
4.Make a file with given permission to read& write to all but no one should have execute permissions.
27. Write a command to find “Finfet is future of vlsi” in a file named XYZ.
28. Create a hidden file & write your favourite actor name.
29. Write a command to find how many times error occurred in your report.

1)Explain physical design flow and also mention input and output files in each stage.
2)What are guidelines of macro placement .Explain need of flyline analysis.
3)What is difference between a blockage and Halos?
4)Can a new master clock be defined at output of th flip flop instead of generated clock .Support your answer with valid explaination.
5)Can there be setup and hold violation on same path?
6) What is difference between target and link library.
7) What is Flip chip floorplan?
8) Explain sanity check related to various stage?
9) what are placement blockages and how it will be useful?
10) what are placement blockages and how it will be useful?
11) what are the inputs to the CTS?
12) why we can solve hold violation in CTS stage only?
13) what is latch up and reducing technique?
14) what is setup and hold violation and reduing techniques?
15) what is clock gating and use of clock gating?
16) what is electron migration and how to reduce EM?
17) What is antenna effect?How to eliminate this?Is there any violation if (Max antenna ratio=400;gate area=1sq. unit;Metal area connecting to gate=500sq. unit)
18) what is DEF file contains?
19)Explain:1.Tap cell 2.Tie Cell 3.End Cap Cell 4.Decap cell 5.Filler cell 6.Spare cell 7.Switch cell.
20)what is difference between Physical library and logical library file.
21)Explain Setup and Hold time with help of waveform . Also explain recovery and removal time.
22)What are PVT Corners ?Why we need to close timing in all these corners?
23)On which factors cell delay depends?
24)What are the different types delays on which we focus mainly during STA?
25)What is virtual clock? How we can say any clock is virtual/ generated/ mastered by looking into sdc. File?
26)How prime time will report if you a
• Set-false path
• Set-disable time
To you design.
27)Explain mmmc. Which parasitic interconnect corners are checked for setup and hold?
28)Draw the waveform for following
• Create_clock –period 1.2 –waveform{0.3 0.4 0.8 1.0} JTAG Clk
29)Explain OCV, Derate and CRPR.
30)Considering interconnect parasitics are not considered here find path delay b/w IN & OUT.

Slew at IN = 10ps
Load at OUT (Ci) = 2PF
I/P pin capacitance (I1 & I2) = 1 PF
Delay Table
Slew at A Load at Y
10ps 40ps 50ps
20ps 50ps 60ps

31)How synthesized netlist i.e. (.v) is in i/p stage of Floorplan is different from RTL netlist?
32)What is clock latency? Explain source & n/w delay.
33)What is setup & hold timing? Derive equation to find setup & hold slack.
34)What are timing exceptions? Why they should be given as constraints?
35)Explain PD flow, i/p & o/p files in each stage.
36)What is uncertainty? Explain inter clock uncertainty.
37)Analyse if there is any violation?Calculate Setup and hold slack in both the ckts.

38)What is use of placement bounds?
39)What is nested Generated clock? Explain with help of example.

With respect to timing report above answer the following questions:
1.What is clock period of SDRAM_CLK?
2.What type of timing analysis it is reporting?
3.If it is A hold timing report then mention the Hold time if it is setup timing report then mention the setup time.
4.Is there any violation .If yes then by what value it is violating?
5.What is significance of path type in this report?

41)what is significance of following clocks:
1.create_generated_clock -name CLK_INV \
-source [get_ports CLK] -divide_by 1 get_pins A/Y
2. create_generated_clock -name CLK_INV \
-source [get_ports CLK] -divide_by 1 [get_pins A/Y] \

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