[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_column_text]Aptitude Questions:
1. Cart A cover a certain distance at the speed of 15 km/hr, another Cart B covers the same distance at the speed of 16 km/hr. If Cart A takes 16 minutes longer than B to cover the same distance find the distance in kms?
A.60 B.62 C.64 D.66

2. Train travels at average speed of 100 km / hr, it stops for 3mins after travelling 75 kms of distance. How long it takes to reach 600 kms from the starting point.
A. 6hrs 11mins B. 6hrs 21mins C. 6hrs 31mins D. 6hrs 18mins

3. A thief is noticed by a policeman from a distance of 200m. The thief starts running and the policeman chases him. The thief and the policeman run at the rate of 10 km and 11 km per hour respectively. What is the distance between them after 6 minutes?
A.90mtrs B.80mtrs C.100mtrs D.120mtrs

4. A walks around a circular field at the rate of one round per hour while B runs around it at the rate of six rounds per hour, They start in the same direction from the same point at 7.30 a.m. They shall first cross each other at:
A. 7:42a.m. B. 7:40a.m C. 7:32a.m D. 7:36a.m

5. If a person walks at 14 km/hr instead of 10 km/hr, he would have walked 20 km more. The actual distance travelled by him is :
A.35km B.40km C.45km D.50km

6. A man performs 3/5 of the total journey by rail, 17/20 by bus and the remaining 6.5 km on foot. His total journey is :
A.130km B.120km C.100km D.110km

7. Sound is said to travel in air at about 1100 feet per second. A man hears the axe striking the tree, 11/5 seconds after he sees it strike the tree. How far is the man from the wood chopper?
A.2240ft B.2420ft C.4200ft D.2600ft

8. A boat running upstream takes 8 hours 48 minutes to cover a certain distance, while it take 4 hours to cover the same distance running downstream. What is the ratio between the speed of the boat and speed of the water current respectively?
A.3:8 B.5:3 C.3:5 D.8:3

9. A man rows to a place 48 km distance and back in 14 hours. He finds that he can row 4 km with the stream in the same time as 3 km against the stream. The rate of the stream is:
A. 1km/hr B. 2km/hr C. 3km/hr D. 4km/hr

10. If each of the three nonzero numbers a, b, and c is divisible by 3, then abc must be divisible by which one of the following the numbers?
A.25 B.27 C.29 D.23

11. What is the least number of Soldiers that can be drawn up in troops of 12, 15, 18 and 20 soldiers and also in form of Solid Square?
A.950 B.925 C.900 D.875

12. In a division sum, the divisor is 10 times the quotient and 5 times the remainder. If the remainder is 46, the dividend is
A.5334 B.5335 C.5336 D.5337

13. The students in three classes are in the ratio 2:3:5. If 20 students are increased in each class, the ratio changes to 4:5:7. The total number of students before the increase were :
(A) 100 (B) 90 (C)10 (D) none of these

14. Raj invested Rs 76000 in a business. After few months Monty joined him and invests Rs 57000. At the end of year both of them share the profits at the ratio of 2:1. After how many months Monty joined Raj ?
(A) 4 Months (B) 8 Months (C) 5 Months (D) 6 Months

15. A trader has 100 kg of rice, a part of which he sells at 30% profit and the rest at 5% profit. He gains 25% on the whole. What is the quantity sold at 30% gain?
(A) 80 kg (B) 40 kg (C) 75 kg (D) 35 kg

Digital Electronics Questions:
16.A monostable multivibrator is commonly called a two shot.

A. True

B. False

17.The microcontroller needs to use only three input lines to monitor eight separate points.

A. True

B. False

18.A 74HC283 can be used to implement a 4-bit full adder.

A. True

B. False

19.
Which of the following commands will copy the contents of RAM whose address is in register 0 to port 1?

A. MOV @ P1, R0

B. MOV @ R0, P1

C. MOV P1, @ R0

D. MOV P1, R0

20.MPGA stands for:

A. mass produced gated array.

B. Morgan-Phillips gated array.

C. memory programmed ROM.

21.What are the typical values of tOE?

A. 10 to 20 ns for bipolar

B. 25 to 100 ns for NMOS

C. 12 to 50 ns for CMOS

D. All of the above

22.List the state of each output pin of a 7447 if RBI = 0, LT = 1, A0 = 1, A1 = 0, A2 = 0, and A3 = 1.

A. RBO = 0, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0

B. RBO = 1, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0

C. RBO = 0, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0

D. RBO = 1, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0

23. Any divide-by-N counter can be formed by using external gating to ________ at a predetermined number.

A. HIGH

B. reset

C. LOW

D. preset

24.Convert 110010012 (binary) to decimal.

A. 201

B. 2001

C. 20

D. 210

25.The ________ is defined as the maximum number of standard logic inputs that an output can drive reliably.

A. fan-drive

B. fan-out

C. fan-in

D. open-collector

26.Temperature variation is normally an analog quantity.

A. True

B. False

27.The ________ circuit overcomes the problem of switching caused by jitter on the inputs.

A. astable multivibrator

B. monostable multivibrator

C. bistable multivibrator

D. Schmitt trigger

28.The 74194 4-bit bidirectional universal shift register has a wide range of applications.

A. True

B. False

29.Of the methods listed, the fastest A/D conversion is done by a ________.

A. single-slope ramp converter

B. dual-slope ramp converter

C. successive-approximation converter

D. tracking converter

30.The holes through a PC board are ________.

A. smaller with SMT than with through-hole mounting

B. larger with SMT than with through-hole mounting

C. the same size as with through-hole mounting

D. usually unnecessary

31.What is an analog-to-digital converter?

A. It makes digital signals.

B. It takes analog signals and puts them in digital format.

C. It allows the use of digital signals in everyday life.

D. It stores information on a CD.

32.
The Boolean equation results from this Karnaugh map.

A. True

B. False

33.Whenever information is transmitted from one device to another, there is a possibility that ________.

A. one device is off

B. errors will occur

C. there is a full moon

D. the data will be received as transmitted

34.Logic circuits that are designated as buffers, drivers, or buffer/drivers are designed to have:

A. a greater current/voltage capability than an ordinary logic circuit.

B. greater input current/voltage capability than an ordinary logic circuit.

C. a smaller output current/voltage capability than an ordinary logic.

D. greater input and output current/voltage capability than an ordinary logic circuit.

35.
Perform the following hex subtraction: ACE16 – 99916 =

A. 23516

B. 13516

C. 03516

D. 33516

PHYSICAL DESIGN QUESTIONS:
TOOL PART:
1.Write commands to do sanity checks before floorplan?
2.Write command to add buffers on net1 using the lib/BUF library cell. The repeater distance is 100 and the first distance is 80.
3. Write a command to add horizontal end cap cells named MY_END_CAP to the current design.
4.Write a command which applies the set_dont_touch_network command to all clocks in the current design
5. write a command which shows the collection of all high-fanout nets from the design having a fanout count of more than 100
6. write a command to check if placement done is ligeal.
7.write a command to check that the current design is routable.
8.write a command that creates a floorplan with a chip boundary, core, rows, and wire tracks
9.diff blw place_opt and psynopt

SUBJECTIVE QUESTIONS:
1.What is difference between a Flip flop and latch?
2.Explain the following theorems :
1.KVL 2.KCL 3.Thevenin 4.Nortans’ theorem
3.Explain the following terms :
1.Die 2.Core 3.Pin 4.Ports 5.Terminals 6.Macros 7.Standard cells.
4.What happens to delay if you increase load capacitance?
5. What is cell-delay?
6. What is net-delay?
7. What is timing-arc?
8. What is setup time & Hold time?
9. What are the components you need to include while doing setup analysis?
10. What are the components you need to include while doing Hold analysis?
11. What is clock-skew?
12. Explain in2reg, reg2reg, reg2out & in2out paths in STA.
13. What are all the different components you see in a reg2reg timing report?
14. Can you tape-out the chip with setup & hold violation?
15. Lets say Setup & Hold is clean, but you’ve DRV violations. Can we tape-out the design?
16. With respect to Realisation techniques of transistors explain the following terms :
1.Crystal Growth
2.Oxidation
3.Photolithiography
4.Etching
5.Diffusion
6.Epitaxial growth
17.Explain working of n-channel enhancement type MOSFET
18.Realise the following Digital circuits
1)D ff using 2×1 mux
2)NAND,NOR using CMOS
3) AND,OR ,NOT using 2×1 mux
4)4×1 mux using 2×1 mux
19.What are guidelines of macro placement .Explain need of flyline analysis.
20.What is difference between a blockage and Halos?
21.Can a new master clock be defined at output of th flip flop instead of generated clock .Support your answer with valid explaination.
22.Can there be setup and hold violation on same path?
23.Why we predominantly use Flip flops over latches in physical design?
24. what is significance of following clocks:
1.create_generated_clock -name CLK_INV \
-source [get_ports CLK] -divide_by 1 get_pins A/Y
2. create_generated_clock -name CLK_INV \
-source [get_ports CLK] -divide_by 1 [get_pins A/Y] \
-combinational
25.Explain mmmc. Which parasitic interconnect corners are checked for setup and hold?
26. What is virtual clock? How we can say any clock is virtual/ generated/ mastered by looking into sdc. File?
27. What is electron migration and how to reduce EM?
28. What is antenna effect?How to eliminate this?Is there any violation if (Max antenna ratio=400;gate area=1sq. unit;Metal area connecting to gate=500sq. unit)
29. what is DEF file contains?
30.Explain:1.Tap cell 2.Tie Cell 3.End Cap Cell 4.Decap cell 5.Filler cell 6.Spare cell 7.Switch cell.
31.what is difference between Physical library and logical library file.
32.Explain Setup and Hold time with help of waveform . Also explain recovery and removal time.
33.What are PVT Corners ?Why we need to close timing in all these corners?
34.What is cloning?
35.What is significance of bounds and placement blockages?
36. what are the inputs to the CTS?
37. why we can solve hold violation in CTS stage only?
38. what is latch up and reducing technique?
39.what is setup and hold violation and reduing techniques
40.Analyse if there is any violation?Calculate Setup and hold slack in both the ckts.

41.
1.Which command will give such an output.
2.Which type of timing analysis is reported here.
3.Is there any violataion ? if yes then what is margin by which it is violating
4.What is timing path that is being analysed here.What type of clock is use to constrain this path?

42.
1.Write a script to get inputs from user and add the num and print sum at console.
2.Write a script to get input as °C from user and convert into °F .
3.WAS to print following patterns

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