Physical Design Evaluation test # 1
Duration: 3 hours
Number of questions: 75
Test date: 11/MARCH/2021,
This test can be attempted from home or institute.
Q1:Explain physical design flow in details.
Q2:What are input files in floorplanning stage?
Q3: NDR rules define non-default rules for routing. Why apply these before placement.
Q4: What is the benefit of having separate path groups for I/O logic paths?
Q5. What does applying a timing critical range do, and what is the benefit of this?
Q6. Applying a weight > 1 to a path group may increase a design’s critical path delay. True or False?
Q7:What are clock tree exceptions?Explain.
Q8:What is skew,insertion delay,latency?
Q9:What are the two main goals of CTS?
Q10. What is the difference between stop and exclude pins? List some examples of implicit stop/exclude pins.
Q11. How is a float pin different from a stop pin?
Q12. What happens when building the CT using min_max?
Q13.Explain Clock tree optimization. Explain different ways of min. skew.
Q14. How do you set a clock skew target of 0.1 for clk1, and a minimum insertion delay of 0.7 for clk2? What is the skew target for clk2?
Q15. Write the command(s) to balance the two clock trees clk1 and clk2, so clk2 arrives 0.3 earlier!
Q16. Why is it important to remove or adjust the clock uncertainty before executing clock_opt
Q17. What is the difference between a Milky way design library and reference library? What do they have in common?
Q18. How to reduce setup violations in placement stage?
Q19. What is insertion delay and different types?
Q20. What is latch up and reducing technique?
Q21 what is clock gating and use of clock gating?
Q22.what is electron migration and how to reduce EM?
Q23. Antenna violation and reducing techniques?
Q24.What is crosstalk.How to avoid cross talk problems?
Q25. what is uncertainity and types of uncertainity
Q26:Why we define Generated clock why can’t we use same master clock on place of it.
Q27.what is difference between Retention cells and isolation cells.
Q28.At which stage we fix hold violations and why?
Q29.What are different types of delay models. Explain.
Q30.If there are two macros whose pins on not in same side then if I abut it ,what kind of DRC violation will I get.
Q31.How addition of tap cells help in CMOS Latchup.
Q32.So on which factors cell delay is dependent.if a cell has multiple pin then how is i/p transition calculated.
Q33.Will addition of buffer can help in Setup violation. If yes then how.
Q34.Which is better buffer and inverters.
Q35.what is content of clockspec.tcl,Explain mining of target skew,global skew,local skew.
a) Single Input NOT
b) Two Input AND
c) Two Input OR
d) Two Input NOR
e) Two Input NAND
f) Two Input XOR
x1x3 + x2x3 + x1x2 = x1x2 + x1x3 + x2x3
The control circuit must produce an output of 1 if at least two of the conditions A, B, and C are true. Design the simplest circuit that can be used for this purpose
F (w1, w2, w3, w4, w5) = w1?w2?w4?w5 + w1?w2 + w1?w3 + w1?w4 + w3?w4?w5
(A)8.16% decrease (B) 8.42 % increase (C) 8.44% decrease (D) 8.18% increase
(A) 425 (B) 525 (C) 500 (D) 450
(A) 1260 (B) 1255 (C) 1270 (D) 1250
(A) 230 (B) 250 (C) 300 (D) 225
a.1 hour b. 80 min. c. 84 min. d. 1 hr 32 min
(A) 200 (B) 80 (C) 40 (D) 120
(A) 0 (B) 2 (C) 1 (D) None of these[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row]
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