[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_column_text]VLSIGuru Institute

**Physical Design Evaluation test # 1**

**Duration: 3 hours**

**Number of questions: 75**

**Test date: 11/MARCH/2021, **

This test can be attempted from home or institute.

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Q1:Explain physical design flow in details.

Q2:What are input files in floorplanning stage?

Q3: NDR rules define non-default rules for routing. Why apply these before placement.

Q4: What is the benefit of having separate path groups for I/O logic paths?

Q5. What does applying a timing critical range do, and what is the benefit of this?

Q6. Applying a weight > 1 to a path group may increase a design’s critical path delay. True or False?

Q7:What are clock tree exceptions?Explain.

Q8:What is skew,insertion delay,latency?

Q9:What are the two main goals of CTS?

Q10. What is the difference between stop and exclude pins? List some examples of implicit stop/exclude pins.

Q11. How is a float pin different from a stop pin?

Q12. What happens when building the CT using min_max?

Q13.Explain Clock tree optimization. Explain different ways of min. skew.

Q14. How do you set a clock skew target of 0.1 for clk1, and a minimum insertion delay of 0.7 for clk2? What is the skew target for clk2?

Q15. Write the command(s) to balance the two clock trees clk1 and clk2, so clk2 arrives 0.3 earlier!

Q16. Why is it important to remove or adjust the clock uncertainty before executing clock_opt

Q17. What is the difference between a Milky way design library and reference library? What do they have in common?

Q18. How to reduce setup violations in placement stage?

Q19. What is insertion delay and different types?

Q20. What is latch up and reducing technique?

Q21 what is clock gating and use of clock gating?

Q22.what is electron migration and how to reduce EM?

Q23. Antenna violation and reducing techniques?

Q24.What is crosstalk.How to avoid cross talk problems?

Q25. what is uncertainity and types of uncertainity

Q26:Why we define Generated clock why can’t we use same master clock on place of it.

Q27.what is difference between Retention cells and isolation cells.

Q28.At which stage we fix hold violations and why?

Q29.What are different types of delay models. Explain.

Q30.If there are two macros whose pins on not in same side then if I abut it ,what kind of DRC violation will I get.

Q31.How addition of tap cells help in CMOS Latchup.

Q32.So on which factors cell delay is dependent.if a cell has multiple pin then how is i/p transition calculated.

Q33.Will addition of buffer can help in Setup violation. If yes then how.

Q34.Which is better buffer and inverters.

Q35.what is content of clockspec.tcl,Explain mining of target skew,global skew,local skew.

**CMOS:**

- Why PMOS is connected to VDD and NMOS is connected to ground in CMOS configuration?
- Draw the circuit for CMOS inverter and write truth table?
- What is Static power dissipation in CMOS?
- What is Dynamic power dissipation in CMOS?
- What is SET UP time and HOLD time?
- What is propagation delay?
- Draw the circuit of CMOS AND gate write the truth table?
- What is short circuit current and leakage current in CMOS inverter?
- Compare the sources of power dissipation between static CMOS and dynamic CMOS circuits?
- Why PMOS aspect ratio is greater than NMOS in CMOS inverter?

DIGITAL:

- How can you implement following gates using a 2:1 MUX?

a) Single Input NOT

b) Two Input AND

c) Two Input OR

d) Two Input NOR

e) Two Input NAND

f) Two Input XOR

- Determine if the following equation is valid

* *

*x***1 x3 **

- A circuit that controls a given digital system has three inputs:
*x*1,*x*2, and*x*3. It has to recognize three different conditions:

- Condition
*A*is true ifis true and either,*x*3is true or*x*1is false*x*2 - Condition
*B*is true ifis true and either,*x*1or*x*2is false*x*3 - Condition
*C*is true ifis true and either,*x*2is true or*x*1is false*x*3

The control circuit must produce an output of 1 if at least two of the conditions *A*, *B*, and *C *are true. Design the simplest circuit that can be used for this purpose

- Implement the function below, by using a 4-to-1 multiplexer and as few other gates as possible. Assume that only the uncomplemented inputs
*w*1,*w*2,*w*3,*w*4, and*w*5 are available.

**F (w****1, w2, w3, w4, w5) ****= ****w****1?w2?w4?w5 ****+ ****w****1?w2 ****+ ****w****1?w3 ****+ ****w****1?w4 ****+ ****w****3?w4?w5**

- Determine the functional behavior of the circuit in Figure below. Assume that input
*w*is driven by a square wave signal. - Design a sequence detector state machine that detects a pattern “10110” from an input serial stream. Use D Flip-Flops.

- Implement following logics using minimum number of D Flip-Flops:
- a) Clock Divide by 2
- b) Clock Divide by 4

- Design a three-bit up/down counter using T flip-flops. It should include a control input called Up
*/*Down. If Up*/*Down = 0, then the circuit should behave as an up-counter. If Up*/*Down = 1, then the circuit should behave as a down-counter.

- Suppose you need a memory array with 1k × 8 organization, but all you have on hand are 1k × 4 memory chips. How to Implement??

- Reduce the expression, A’B’C’ + A’BC’ + A’BC
- Find the min-term expansion for F (A, B, C) in the diagram below
- Consider function f, as implemented below. Re-design the circuit using only 2-to-1 multiplexers. Use at most seven such multiplexers and no other logic gates.
- Diagram explanation: 4 AND gates in 1st stage(3 X 3 inputs and gates, 1 X 2 input AND gate), 2nd stage(all outputs of 4 AND gates are input to OR gate), which is the final output.

- Design a mod-5 counter which has the following binary sequence: 0, 1, 2, 3, 4.
- Design a counter with the following repeated binary sequence: 0, 4, 2, 1, 6. Use T flip-flops
- Implement logic circuit for a block, which multiplies 3-bit number (
**A2, A1, A0**) with a number**3**.

**APTITUDE:**

- If a number is increased by 12% and then decreased by 18%, then find the net % change in the number.

(A)8.16% decrease (B) 8.42 % increase (C) 8.44% decrease (D) 8.18% increase

- The value of a machine depreciates at the rate of 20% every year. It was purchased 2 years ago. If its present value is 6400, its purchase price was
- 9240 (B) Rs.7920 (C) Rs.6400 (D) Rs.10000

- In a test minimum passing percentage for girls and boys is 35% and 40% respectively. A boy scored 483 marks and failed by 117 marks. What are the minimum passing marks for girls ?

(A) 425 (B) 525 (C) 500 (D) 450

- A person incurs 5% loss by selling a bat for Rs 1140. At what price should the watch be sold to earn 5% profit?

(A) 1260 (B) 1255 (C) 1270 (D) 1250

- A man buys 5 horses and 7 bulls for Rs 1950 he sells the horses at a profit of 10%and bulls at a profit of 16% and on the whole his gain is Rs 237 what price does he pay for a horse?

(A) 230 (B) 250 (C) 300 (D) 225

- Sumit and Ravi started a business by investing Rs 85000 and 15000 respectively. In what ratio the profit earned after 2 years be divided between Sumit and Ravi respectively?
- 17:1 (B) 17:2 (C) 17:3 (D)17:4

- The Value of a machine depreciates 10% annually. If the present value of the machine is Rs 1, 00, 000/- then the total depreciation during 2 years hence will be?
- Rs 81, 000 (b) 21, 000 (c) Rs 19, 000 (d) Rs 72, 000
- Two pipes A and B can fill a tank in 1 hour 12 minutes and 1 hour 30 minutes, respectively. Pipe C can empty the tank in 1 hour. Initially, Pipes A and B are opened and after 14 minutes C is also opened. In how much time will the tank be full? (L-2)

a.1 hour b. 80 min. c. 84 min. d. 1 hr 32 min

- The average age of 5 members is 21 years. If the age of the youngest member be 5 years, find the average age of the family at the birth of the youngest member
- 20 years (B) 19 years (C)13 years (D) None of these
- A man can complete 3/8 of a work in 24 days . At this rate, how much more time is required to complete the work?
- 15 days b. 40 days c. 64 days d. 28 days

- Mr. X can complete a job in 18 days , Mr.Y in 20 days and Mr. Z in 30 days , Mr. Y and Mr.Z start the work and are forced to leave after 4 days . The time taken to complete the remaining work by Mr.X is
- 12 days b. 18 days c. 20 days d. 26 days

- A man and a woman 81 miles apart from each other, start travelling towards each other at the same time. If the man covers 5 miles per hour to the women’s 4 miles per hour, how far will the woman have travelled when they meet?
- 27 b. 36 c. 45 d. none of these

- A bus without stopping travels at an average speed of 60 km/hr and with stoppages at an average speed of 40 km/hr. What is the total time taken by the bus for stoppages on a route of length 300km?
- 3 hr b. 4 hr c. 2.5 hr d. 3.5 hr
- Three numbers are in the ratio 3 : 4 : 5 and their L.C.M. is 2400. Their H.C.F. is:

(A) 200 (B) 80 (C) 40 (D) 120

- Find the unit’s digit in (5314)
^{98}+ (7454)^{151}?

(A) 0 (B) 2 (C) 1 (D) None of these[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row]