SESSION#1 (04/MAY/2021)

1. hardware design
   • Significance of Transistor
2. hardware design
   o EDA : Electornic design automation

ex:
o Mobile phone SOC(System On Chip)
o requirements
o what do we want out of mobile phone
o architecture
o high level and low level design
o RTL design team: They develop Verilog code of the design
o Functional verification to check whether Verilog code is working fine
o Synthesis
o Verilog RTL code —> Synthesis tool(Design compiler) —> Gate level netlist
o Gate level netlist: Using logic gates
o ex of logic gates: and, or, xor, nand, nor, not, buf, etc
o Gate level netlist is taken through the VLSI backend flow
o Physical design
o DFT
o STA
o IR drop analysis
o Custom layout
o Physical verification
o We extract GDSII out of this netlist
o given to fabrication company => Chip
o Post silicon validaiton done on chip.

3. Why we are studying CMOS, transistor?
4. Simple ex: Up counter
   o gate level
   o transistor
5. Verilog language : specially meant for implementing the design behavior
   o 4 abstraction levels => 4 styles
   o behavioral(algorthmic) style of coding
   o Data flow(RTL) style of coding
   o Gate level(structural) style of coding
   o Switch level(pmos, nmos, fet) style of coding
6. up counter
   • counts up wards
   • 3 bit up counter
7. people will talk about RTL coding, behavioral coding
   what is this behavioral coding??
8. 100% of the design in the world are implemnented using Behavioral style of coding only
9. where are the gates ? where are the transistors?
10. we will take example of upcounter, how the gate level representation will look like
    o how do we implement a design using gate level?
    o understand the design behaviour
    o write the truth table
    o use k-maps to come up with the boolean expression
    o boolean expression can be implemented using logic gates(gate level representation)
    o custom layout engineer: These logic gates are converted in to transistor level implementation
    o we can fabricate the transistor level representation of the chip
11. where is transistor coming in to the picture?
    o if we purchase a mobile phone or laptop
    o chip inside these devices consists of only transistors(billions of transistors)
    o where is the transistors?

Inverter:
– Inverter fabricated using CMOS technology requires 2 transistors : 1 PMOS, 1NMOS
2 input NAND:
– how many transistors required: 4 (2 pmos, 2 nmos)
a b y
0 0 1
0 1 1
1 0 1
1 1 0
– NMOS:
if gate voltage=high => switch will be on
if gate voltage=low => switch will be off
– PMOS:
if gate voltage=high => switch will be open(off)
if gate voltage=low => switch will be on

12. transistor is also called as a switch
13. CMOS : Complementary MOSFET
    o Complementary: same circuit requires implementing both PMOS and NMOS
    o if we use one PMOS, we must use one NMOS
    o in CMOS technology, if there are 100 PMOS transistor, how many NMOS will be tehre? 1000

VDD: logic 1(logic high)
Gnd(VSS): logic 0 (logic low)

14. Basically NAND gates requires 4 switches(forget transistors) o which will behave as below
    • N-switch:
      if gate voltage=high => switch will be on
      if gate voltage=low => switch will be off
    • P-switch:
      if gate voltage=high => switch will be open(off)
      if gate voltage=low => switch will be on

what technology we can use to implement these switches?
o

15. Mobile phone SOC
    o how do we implement the design behavior?
    Verilog behavioral style of coding
    o consists of 100000’s of line of Verilog code
16. upcounter
    Verilog code : 4 lines
    gate level representation: 3 inverter + 3 AND + 1 OR + 1 XOR + 3 Flipflops(each Flipflop requires 8 NAND + 2 NOT)
    = 38 gates
    roughly: 4 lines of Verilog is getting synthesized in to 38 gates
    it doens;t mean that 40 lines => 380 gates(not always)
    each line converting to 10 gates Mobile phone SOC code: 10 lakhs lines => 100 lakh gates(rough estimate)
    we need to fabricate these 100 lakh gates on to the chip => then that chip will behave like a mobile phone SOC if we can come up with an efficient way of representing the basic gates(inverter, And, OR, xor, nand, nor) using some switch level logic
    o then we can implement complete mobile phone SOC using the same technology
    100 lakh gates => it only consists of the basic logic gates(inverter, buffer, and, or, xor, nand, nor, xnor) what do we mean by ‘efficient way’ of representing the basic gates?
    o performance should be good
    o low power consumption
    o it should consume less area, it should cost less
    o behavior should be stable at different temprates, voltages and lower technology nodes why area is important?
    o if NAND requires 100 SQ nm of area (100*10-9 Sq) o 1 crore NAND gates => total area = 107 * 100 Sq nm = 10**9 sq nm o anotehr technology, which consumes only 50 SQ nm for NAND gate total area = 5*10**8 sq nm overall chip area comes down o we can manufacture double teh chips in same die area o per chip cost comes down by half amount o company can sell the final product at lesser cost and can still make profit out of it. 350nm -> 180nm -> 90nm -> 60nm -> 45nm -> 28nm -> 22nm -> 14nm -> 10nm -> 7nm -> 5nm -> 3nm
    o IT IS ONLY ABOUT HOW TO REDUCE THE COST PER CHIP, HOW TO REDUCE THE SIZE OF THE CHIP. India: 5 -> 50 degress
    same mobile phone => Russia(-30 o), Africa(57 degrees) => phone should still work without any issues
17. what do we mean by ‘efficient way’ of representing the basic gates?
    o performance should be good
    o low power consumption
    o it should consume less area, less cost
    o behavior should be stable at different temprates, technology nodes and diffeernt voltage conditions VLSI industry is finding way to achieve above 4 requirements?
    BJT -> Current controlled device
    as we move to lower technologu
    BJT is not good at lower technology nodes Field effect transistors(voltage controlled devices) JFET MOSFET PMOS NMOS CMOS => short channel effects good till 28nm once we go below 28nm => CMOS has a problem of short channel effects(multiple effect) to mitigate this problem, industry moved to FinFET technology, which reduces the problem of short channel effect FinFET o this is the technology used in the latest electnoics devices
18. how to implement a gate using switches(transistors)

NAND : requires 4 switches
o how to fabricate these switches? which technology will give best of above 4 factors?
o lets start with a mechanical switch
o it is not possible to manufacture crores of mechnical switches
o how to control these many switches(crores of them)
o impact on area
o Semiconductor based switches
o which can be controlled using current or using voltage
BJT: current controlled device
if we apply specific current level at Base => it will result in current flowing from Emitter to colletor ==> switch is on.
if we don;t apply current at Base => there will not be any flow of current between Emitter and collector ==> switch is off.
since we are able to decide switch on and off using application of the current at base of teh BJT => BJT is called as Current controlled device.

    o To represent any logic gates, we require Switch behavior
        o switch can't be implemented using mechanical devices(ex: water tap, current swtiches)
        o instead we need very tiny swtiches
            o which are easy to manufacture
            o each to control
            o consumes less power
            o consumes less area
            o efficeient at various temparatures, voltages, technology nodes
    o BJT
        o can act like a switch
    o CMOS
        o NAND using CMOS technology
        o We understood how PMOS and NMOS behaves like switches
            o are these current controlled or voltage controlled devices?
                o by applying voltage the gate of the pmos or nmos, we are able turn on/off the switch.
                o it starts behaving badly for technology nodes below 28nm
                    o short channel effects
    o to mitigate short channel effects, we moved to FinFET technology

19. 3 kinds of solids
    o conductors
    o semiconductors
    o insulators

lets say, source, drain, substrate is implemented using conductor?
o source and drain will always be connected, we won’t be able to control the flow
o hence it won’t behave like switch

lets say, source, drain, substrate is implemented using insulators?
o current will never flow
o switch will always be off

we need a special element which behaves at one point like a conductor and at other point it should behave like an insulator
o that kind of special element is called as ‘semi-conductor’
o when we can get this kind of on behavior in one case and off behavior in other case => we can acheive switch behavior out of it => hence we use semi-conductor to implement source, drain and substrate.

20. conduction band => band where flow of current happens
    valance band => every atom needs to complete its valance
    o 2, 8, 18
    o every atom achieves stability by pairing with adjacent atom by ensuring it has valance number of electrons around it.
    o it is difficult to break electrons out of this valance bond
    o when any atom has number of electrons associated with it as 2/8/18, it is very difficult(we need to apply lot of energy) to break an electron out of such atom. conductor(copper, Aluminium): voltage that we apply is good enough to break some of these valance bond between atoms => which creates free electrons, since valance band and conduction band are overlapping => these electrons(which got free due the voltage applied)
    o these electrons which are in conduction band, will contribute to the flow of current.
    when we increase the voltage from 5V to 100V => more valance bonds between atoms will be broken => more free electrons gets created => these electrons will jump to to conduction band => they result in higher current

SESSION#2 (05/MAY/2021)

revision:

1. hardware design flow
   o algorthmic
   o synthesis => gate level netlist
   o gate level(structural modeling)
   o directly developing gate level netlist
   o this gate level modeling can only be done for smaller design, may be less than 100 gates.
   o in both the approaches, the output is a gate level netlist
   o netlist is input complete backend flow.
2. How to implement a logic gate using switches
   o how to implement a switch
   o Mechanical switch
   o BJT
   o FET
   o JFET
   o MOSFET
   o FinFET
3. MOSFET
   o Elements of a MOSFET?
   o Gate
   o MOI
   o Source
   o Drain
   o Substrate(Base)
4. Source, Drain and Substrate needs to be implemented using Semiconductor
5. What is differnce between conductor, insulator and Semiconductor
   o free electron
   o valance band
   o valance electrons
   o 2, 8, 18
   o conduction band
   o forbidden band
   o enery difference between valance band and conduction band
6. Current flow in any solid happens though the free electrons
   o if a electron breaks out of the valance bond => it creates a hole
   o free electron and holes contribute to the flow of current.
   o for current to flow, we need to apply voltage across the solid
   o as we increase the voltage, free electrons in a conduction increases linearly, hence current also increases linearly.
   current proportional to free electrons.

Agenda:

1. Semiconductors
2. Types of Semiconductors
   o intrinsic
   o extrinsic
   o doping
3. Si, Ge
4. Diode (PN junction)

Notes:

1. N type semiconductors
   o the 5th electon which is not bonded through covalent bond, it free to move around
   o hence called as free electon
   o this is available for flow of current.
2. current is two types
   o drift
   o diffusion
3. If you have 2 solids connected to each otehr, one with high concentration of electrons, these electrons tend to move in to other solid(which has lower electrons concentration), this concept is called as diffusion.
   o in this case, electrons are moving in to other solid(semiconductor) even without applying any electric field ==> diffusion
4. from any element, if we take out electron(it comes out of the valance band), the element has more protons than electrons => +ion
5. from any element, if we fill hole with electron from otehr atom, the element has more electrons than protons => -ion
6. Diode
   PN Junction
   o take an intrinsic semiconductor
   o pure semiconductor
   o one side of it, dope using G-3 element
   o other side of it, dope using G-5 element
   o what we get is a PN junction -> Diode

P-type
majority: holes
minority: electrons (covalent bond breaks, it creates free electrons, which are much lesser in count => minority carriers)

7. When two semiconductor are connected one with higher concentration of electrons and otehr with higher concentration of holes
   what happens?
   Holes in P type semiconductor will move in to N-type semiconductor
   Electrons in N type semiconductor will move in to P-type semiconductor
   Above phenomena happened due to the concept of ‘diffusion’
   it doesn;t require any electric field or any external force.

in any type of device, if there is p semiconductor and there is a n-semiconductor => it they are connected as a junction, always diffusion happens by default.

How much diffusion will happens?
o depletion region

PN junction that is formed after movement of electrons and holes is depelted(not having) of free electrons and holes => hence it is called as Depletion region.

8. depeltion region has 2 sides
   o one is positively charged
   o one is negatively charged o when there is postive charge and negative charge separated by a distance?
   o what does this result in?
   o Electric field
   o what direction?
   + charge to the – charge
   o electric field established in the depletion region does not allow holes and electrons to diffuse beyond specific point.
   o what is that specific point?
   o 0.7V field gets established => it doesn’t allow further diffusion.
   o electrons and holes need atleast 0.7V energy to cross that barrier and move in to other region.
   o whenever p and n junction is made, it automatically results in depeletion region(without any field or user invention)
9. what is current?
   flow of electrons and holes
   current direction is opposite to the direction of flow of electrons
   current direction is same direction of flow of holes
10. forward bias
    p side connected : higher potential
    n side connected : lower potential holes have tendency to go from higher to lower potential
    o we are talking about holes available in P type semiconductor
    electorns have tendency to go from lower to higher potential
    o we are talking about free electorns available in N type semiconductor
    how much potential is required for electorns and holes to cross this deletion region?
    o voltage created by the depletion region(0.7V)
    o when we applied an external voltage of more than 0.7V, electorns and holes have enough energy to cross the depletion region.
    once we have applied voltage more than teh depletion region field, the majority carries in both sides have enough energy to cross the other region due to diffussion.
    o this results large forward current which is exponential once voltage cross 0.7V barrier.
11. PN junction has a depletion region getting created, which is 0.7V incase of Silicon, 0.2V/0.3V incase of Ge If I connect 100 PN junction back to back => will it results in 70V?
    o it doesn’t

SESSION#3 (06/MAY/2021)

revision:

1. Different types of solids
   o conductor, semiconductor, insulator
   o valance band
   o forbidden band
   o conduction band
2. Diode
   o PN junction
   o forward bias
   o zero bias
   o reverse bias
   o V-I charecteristics
   o both the forward and reverse
3. Barrier voltage: small
   reverse breakdown voltage: very high(50 V)

notes:

1. solids have a concept of breakdown
   what is breakdown?
   o insulator
   o by applying sufficient voltage, we can make insulator all to behave like a conductor
   o breakdown voltage is the voltage that makes the insulator behave like a conductor
   o PN diode
   o Si has covalent bond with adjancent Si atoms
   o These bonds can be broken by means of thermal fluctuation or exitation
   o free electron is created, hole is also created
   o reverse bias
   o very high voltage is applied for reverse bias
   o this voltage is so high, that it gives electorn and holes speed increases
   o these electonrs furtehr creates more electonrs by colliding with other atoms => avalanche effect
   o threshold voltage where this effect happens, is called as breakdown voltage.
2. BJT
   • types of BJT
     npn, pnp
   • how BJT functionality is related to a Diode
   • working principle of BJT
     o why is it called current controlled device
     o by applying a small current at Base terminal, we are able to large flow of current(drift current) between E and collector
   • what is alpha, beta
     alpha = IC/Ib (amplification)
     beta = IC/IE (how much collector is able to collect out the carriers given by emitter)
   • how BJT works as a switch(VLSI) and amplifier(Analog applications)
   • why BJT is not used for lower technology nodes
   • BJT different configurations
   • fabrication steps of BJT
3. BJT : Bipolar Junction Transistor
   Bipolar: Both Electrons and holes contribute to the flow of current in BJT, hence called as Bipolar.
   Junction: We are connecting two Diode in cascaded manner
   Transistor: It has resistance which varies based on current applied
   o for some current level, it acts like a insulator(very high resistance)
   o for other current level, it acts like a conductor(very low resistance)
4. in real life, we don’t join two diodes to get BJT.
   we starts with P type or N type base semiconductors, on that we do different fabrication steps, to get BJT structure.
   BJT = DIODE + DIODE (only for understanding purpose)
5. BJT works in 3 regions
   o Active region
   o Transistor acts as an amplifier
   o Saturation region
   o Transistor is fully on, operating as a switch
   o cut off region
   o Transistor is fully off, Ic = 0
6. BJT can act like a switch and can also act like a amplifier
   o how BJT acts like a switch?
   o ON
   o it should result in flow of curretn
   o OFF
   o it should result in curretn cutoff

BJT : is about flow of charge carriers from E to Collector
o for that flow to happen, path must be closed.
o PN junction at B->E has a depletion region
o When we apply B with E+0.7V, we are applying enough voltage across PN junciton to remove the depletion region. Now the switch gets closed due to this.

Drift: flow of carries due to voltage applied
o NPN : Holes will be contributing to the collector to emitter current
o electrons are contributing to removing teh depletion region
o electrons: majority charge carriers
o holes: minority charge carriers => contribute to the flow of current

7. IC fabrication
   o Doping
   o Etching
   o removing of specific element(oxide)
   o Lithography
   o Oxide deposition
8. fabrication
   o doping
   o adding impurities
   o doping itself is two types
   o lightly doped => smaller number of free carriers
   o highly doped => n+/p+ => large number of free carriers
   o n+ => highly doped with penta valent
   o P+ => highly doped with tri valent
   o oxidation
   o Creating SiO2 layer, to create capacitor of the MOSEFT by depositing Polysilicon
   o it can also be used during doping, so that we can only dope specific portion of the silicon only
   o lithography
   o use a mask, apply the beam of UV light on the silicon wafer coated with a thin layer of material called as resist.
   o resist undergoes chemical transformation
   o chemical transformation enables, add and remove as part of deposition and etching.
   o etching
   o process where Sio2 portion is removed
   o during this process we use lithography to etch teh portion SiO2
   o mask
   o used during the lithography
   o resist
   o required during the etching
   o photoresist is helping Hydrofloric acid not to impact Oxide layer
9. Si chip
   biilion transistors in 1 sq cm
   each transistor: 100 sq nm
   can we manually remove oxide by using any mechanical process.
10. if you know BJT, how to model simple logic gates using BJT?

• NAND

7. Field effect transistors
   o transistor switches on and off based on voltage(field) applied across two terminals
   o in BJT, it was based on flow of current at base->E
   o FET: Unipolar
   o NMOS => Electrons are the only carriers
   o PMOS => Holes are the only carriers
8. Depletion mode
   o channel is already present => by default switch is on
   o by appluing voltage at the gate, we deplete the channel => then switch will turn off.
9. enhancement mode
   o channel is not there
   o by appluing voltage at the gate, we create the channel => then switch will turn on. => enhancement mode
10. JFET terminals
    o Gate
    o by applying voltage at the Gate, we can control the flow of current between source and drain
    o Source
    o Drain
11. JFET working principle
    o If we lower voltage applied at the P terminal compared to N terminal(S), P side the of junciton is at a lower voltage compared to N side
    o as we further lower this voltage, the depletion region at P-N junction further increaes
    o at point, depletion region from both pn junction, merges with each otehr, this creates scenarios where, there are no free electons available in that region(complete deplection), hence channel is cut off.
12. Wherever there is P-N junction, it acts like a diode.