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Questions: 30
Marks: 90
Duration : 3 hours (please distribute the time for each question accordingly, each question carries 3 marks)
1. What is Physical Design? How does it differ from RTL Design & coding? List down various steps in PD flow?
2. What are the factors considered in Physical Design implementation flow?
3. Why current technologies are implemented using FinFET technology? List down key differences between BJT, NMOS, CMOS and FinFET.
4. Difference between current controlled transistors and voltage controlled transistors?
5. What is CMOS latch up and how shielding helps?
6. List down various elements that make up the die area?
7. What is a macro? list down key differences between soft macro and hard macro?
8. List down various inputs file for Physical design implementation flow? Write the significance of each of these files in brief.
9. What is setup time & Hold time? Explain using DFF and timing diagram
10. Explain the various steps to fix the setup time violation and Hold time violation.
11. What does PVT refer to? Significance of Physical design engineer?
12. What is metal layer? why we should use multiple metal layers in PnR implementation? what happens if we use only one metal layer for complete flow.
13. What is resistance? what is capacitance? what is parasitic capacitance? Draw a RC circuit for current – voltage relation diagram? Explain how this diagram differs with R & C values changes?
14. What are the steps followed in PnR flow to reduce(or increase) the resistance, to reduce the capacitance?
15. List down various types of delays in Integrated circuits? Explain the significance of Resistance and Capacitance on timing delay values?
16. What is a flipflop and how it different from latch? Explain how setup time & hold time for flipflop is calculated using switch based flipflop implementation(how do we arrive at setup time and hold time number for a FF)
17. Explain difference between Base tapeout and metal tapeout? What is ECO? What is the significance for PD engineer?
18. What is Static Timing Analysis? What are the inputs for STA?  What are the timing arcs in STA? How it differs from functional RTL simulations? Why should we run STA?
19.  What is false path & multi cycle paths in STA? Explain using diagram?
20. What is a voltage domain, power domain and clock domain in SOC
21.  How clocks are generated in SOC? What is XO clock? Explain how clock distribution works in SOC? What does clock selection, multiplexing are used for?
22. What is design netlist and how it differs from design RTL code. What is SDF file. What is the format of SDF file
23. Explain different corners in STA analysis? what is best case and what is worst case? list down differences
24. Explain different types of power consumption in ICs? Significance for Physical Design engineer. Why power consumption reduction is important. What happens if there is significant power consumption.
25. What are the steps taken to reduce the static power consumption and steps taken to reduce static power consumption
26. What are the steps taken to reduce the dynamic power consumption and steps taken to reduce dynamic power consumption
27. Explain following keywords used in PnR flow?

28. Draw the CMOS diagram indicating B,S,G,D,O. Explain N-Well continuity using above diagram? Why is it done?

29. Explain various 2nd order effects in CMOS technology? How they are avoided in physical design flow? (Ex: how shielding is done by PD engineer, it is to avoid CMOS latchup)

30. Write down RTL code for a circuit with DFF output connected to inverter. Implement the same using gate level implementation.[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row]

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