1. Significance of TD bit in packet header?
  2. Why only Memory Write transactions are posted and why not IO Write transactions?
  3. Difference between PCI and PCIe [PCI express]?
  4. In which state of LTSSM, Gen 2 and Gen 1 speeds of different PCIe links handled?
  5. Why 8b/10b encoding in PHY?
  6. Why PCIe is a serial protocol, why not parallel?
  7. What is the size of IO read packet’s requested data?
  8. Which layer of PCIe has flow control mechanism?
  9. Explain flow control mechanism
  10. Difference between InitFC and UpdateFC DLLPs?
  11. Difference between Cfg0 and Cfg1 packets,read or write ?
  12. Difference between PCIe and RapidIO [SRIO]?
  13. What is enumeration in PCIe?
  14. What are the functions performed by software layer in PCIe?
  15. Difference between gen 2 and gen 3 PCIe protocols?
  16. Functions of transaction and data link layers?
  17. How FC credits mechanism works?
  18. Difference between posted and non-posted transactions?
  19. What is split transaction mechanism in PCIe?
  20. Why do we need DLLPs?
  21. How to corrupt PCIe packets?
  22. Different types of routing mechanisms in PCIe?
  23. How message packets are routed?
  24. What is implicit routing?
  25. Which types of packets are routed by ID?
Course Registration