1. List down differences between configuration header for switch and endpoint?
  2. Write the PCIe PIPE architecture?
  3. List down various component of PIPE and functionality of each component?
  4. What are the major differences between PCIe Gen3 & Gen4?
  5. How does PCIe gen4 handles signal integrity issues related to higher data rates at Gen4?
  6. List down various PIPE interface signals?
  7. How does upsizing work in PCIe? What is the role of DLL & PL in upsizing?
  8. What is sublink in PCie? What are the steps required to achieve this?
  9. What is the significance of ByteCount in TLP header?
  10. What is the significance of BCM in TLP header?
  11. How PCIe handles ECRC failures?
  12. How Port arbitration differs from VC arbitration?
  13. Why we need BAR registers for Switch, when we do write/reads to memory or IO in devices only?
  14. What is the difference between prefetchable memory and non-prefetchable memory? How it impacts the protocol efficiency?
  15. List down 5 types of capability registers in PCIe Configuration headers and their significance?
  16. What are the different components PCIe TL design architecture? What are the interfaces required to implement TL?
  17. What is the TL transmit and descriptor structure? What is the significance of descriptor in PCIe data transfer?
  18. Write the Sequence item code for DLL UVC connected to Physical layer on PL – DLL interface (PL is the DUT, DLL is the agent)
  19. List down various tests for Transaction layer DUT verification?
  20. How PCIe verification will differ at module level and SOC level? What are aspects checked at SOC & at module level.
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