Explain various features implemented in logical & electrical sub blocks of Physical Layer?
How scrambling differs from encoding?
What is skew? How do we achieve de-skew? What are the risks if de-skew is not done periodically?
Explain difference between Logical idle and electrical idle? Why do we need logical idle, when electrical idle can give maximum power saving?
What are the various link parameters achieved during link training? Map them to various states of link training.
What is the structure of EIEOS in Gen2 & Gen3. Why there is a difference in structure in both generations.
What are special symbols in Gen2. List down 10 special symbols and their significance
What is polarity and disparity? How does these impact the link data transfers?
List down detailed steps in Link training from the device is connected, i.e steps from Detect to L0.
What is the significance of Polling.Compliance? What is the significance of modified compliance pattern? Write down the compliance pattern symbols.
What is De-emphasis? How it differs between Gen2 and Gen3?
Difference between PAD and IDL symbols in Gen2? Gen3 does not have PAD symbols, who fulfils the role of PAD in Gen3?
What is elastic buffer in PCIe Physical layer? Why is it required?
What is DC balance? Why is it importance to achieve DC balance?
It is important to maintain signal integrity during data transmission? What are the various techniques(parameters) used to achieve this in PCIe Physical layer(electrical)
Why data symbols are distributed on all lanes, whereas OS’s’ are replicated on all the lanes?
Let’s say, we have connected a 5GT/s capable device to another device capable of 8GT/s. What will be final speed of link. What are the various steps involved in achieving the speed of link, starting from Detect till speed is changed to final speed.
What are the sub states of Configuration and significance of each state
What is lane reversal, why is it significant in link training. What happens if lane reversal is not understood by the other side of link.
What is difference between various low power states in LTSSM. How L2 state differs from Disable.
What is Beacon symbol in PCIe, why is it required?
What is FTS? Where do we use this? What N_FTS? How does both link partners agree for N_FTS?
What are different ways to diagnose link failures in PCIe? What is the significance of Loopback state in link diagnosis. How does link know which is loopback master and which is slave?
What is Hotreset state in LTSSM, how it differs from PoR?
What is function level reset in LTSSM. How do we achieve it. Is it possible for end device to reset Root complex?
What is the significance of B:D:F? why these are importance? What would be the limitation if we do not use these?
Configuration and Recovery has Idle sub states, what is the significance of these?
L0s sub states differ for receiver and transmitter? Why do they differ?
How does initiating device know how to go to L0s, L1 or L2? How does target device know whether to move in L0s, L1 or L2? What is the significance of EIOS in these state transitions?
Link can move from L0 to Recovery for various reasons, list down those.
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I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.
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