1. List down differences between 8b/10b encoding and 128b/130b encoding.

2. What are framing tokens in Gen3. Why they are not used in gen2?

3. Explain Data blocks and ordered set blocks in Gen3.

4. Explain all the functionality involved in various layers for initiating data transfer of 100kb

5. What is the structure of TS1 Ordered set. 

6. Explain different states of DLCMSM. What is flow control. How is it related to virtual channel initialization. 

7. Explain the significance of DLL in TLP transfers. 

8. Explain ack and Nak dllps significance 

9. Explain the significance of credits in TLP transfers. List down various types of credits. 

10. Pcie supports byte level unaligned transfers. Explain this using an example. 

11. Pcie root complex does the memory mapping during enumeration. How BAR registers are used during address mapping assignment. 

12. Explain various fields in TLP header. What is the significance of format and type fields 

13. List down various types of TLPs and their routing styles. 

14. Configuration TLPs use ID routing. Why it can’t use address routing. 

15. Explain the role of cfgrd0/1, cfgwr0/1 during the enumeration. Explain using detailed example how complete enumeration is achieved from the time device is connected till enumeration complete

16. List down detailed structure of various TLP Headers for memory, IO, cfg and messages 

17. List down various types of implicit routing

18. What is the significance of attr_1 and attr_0 in TLP header 

19. Explain retry mechanism in DLL. Why is it required 

20. How virtual channels are implemented in PCIe

21. What is significance of TAG and externded tag in TLP header

22. How completion TLP routing happens 

23. What is overhead in TLP transmission. Explain this using an example by arriving at sample overhead numbers 

24. What is updateFC, why is it required. How do we arrive at UPDATEFC frequency. 

25. What is link error. How it is handled in pcie. 

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