1. Explain difference between on-chip protocols and peripheral protocols?
  2. Why on-chip protocols are limited by frequency?
  3. What are the major differences between SPI, I2c protocols with respect to PCIe?
  4. Explain the PCIe topology and various components in PCIe topology?
  5. What is enumeration? What are the types of TLPs used during enumeration?
  6. What is the significance of configuration headers in enumeration?
  7. What is BAR registers, who sets the value of BAR registers?
  8. What is difference between upstream device and downstream device?
  9. We want to transfer 100KB image from Laptop RAM to storage device connected using PCIe. Explain the various aspects that are implemented in different layers of PCIe of each device in the path?
  10. Explain various layers in PCIe and how different functions are distributed in these layers?
  11. Draw a timing diagram for PCI write transaction for burst length of 4
  12. What is full bus mastering, what is compulsory requirement in each device for this to work
  13. What are the limitations of PCI protocol and any other onchip protocols
  14. What is the maximum BW that can be achieved using PCIe Gen4. Show using calculations.
  15. What is difference between TLP, Link packet and Physical Packet?
  16. What is need for encoding in Physical layer?
  17. What is need for scrambling in Physical layer?
  18. What is the role of LTSSM in PCIe communicaiton protocol ,*0
  19. What is TC-VC mapping, how does it help acheive QOS
  20. What are types of arbitration used in PCIe topology to acheive QOS
  21. What is Isochronous transfers and asynchronous transfers, how they differ
  22. List down various types of TLPs and what is the signifinace of these TLPs
  23. What is the signifiance of attr_1_0 and attr_2 bits in PCIe header. What is snoop bit
  24. What is the significance of 3DW TLP header and 4DW TLP header. Where do we need 4DW header?
  25. List down various types of routing used in PCIe.
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