[vc_row][vc_column][vc_tta_tabs style=”modern” active_section=”1″][vc_tta_section title=”Overview” tab_id=”1541971500613-0ec4fc59-2bfc”][vc_column_text]VLSI Online course in Functional Verification (VG-VTO) is a 26 weeks course structured to enable engineers develop expertise in all the aspects of functional verification including ASIC flow, Advanced digital design, STA, CMOS, Verilog, Systemverilog, UVM, Linux OS, PERL/Python scripting, SOC Design and verification and revision management. Online VLSI course is custom designed for online student requirements with theory and lab session timings specifically scheduled at convenient timings. Students are also provided with access to recorded videos for quick revision.

Course includes 9 hands on projects based on Verilog, Systemverilog and UVM, which provides participant with deep insight in to VLSI design and verification aspects. Every aspect of course is supported with detailed examples helps participant with better understanding. Course also covers multiple industry standard projects based on AXI, AHB and Memory Controller. All projects are executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VG-VTO.

• ASIC flow
• Advanced digital design
• Verilog for design and verification
• Systemverilog course, UVM course
• AXI3.0 Protocol, AXI VIP Development
• Memory Controller Functional Verification
• UVM & OVM Language Constructs with with detailed examples
• AHB Protocol, AHB UVC development & AHB I/C functional verification
• Register layer development for USB2.0

[/vc_column_text][/vc_tta_section][vc_tta_section title=”Syllabus” tab_id=”1541971500620-de7bef0f-b03a”][vc_toggle title=”ASIC Flow”]

• Specification
• RTL coding, lint checks
• RTL integration
• Connectivity checks
• Functional Verification
• Synthesis & STA
• Gate level simulations
• Power aware simulations
• Placement and Routing
• DFT
• Custom layout
• Post silicon validation

[/vc_toggle][vc_toggle title=”Advanced Digital Design”]

• Digital Design basics
• Combinational logic
• Sequential logic, FF, latch, counters
• Memories
• Refer to Advanced digital design training page for detailed course contents
  • www.vlsiguru.com/digital-design-complete

[/vc_toggle][vc_toggle title=”Verilog for Design and verification”]

• Verilog language constructs
• Verilog design coding examples covering more than 20 standard designs
  • www.vlsiguru.com/verilog-training/

[/vc_toggle][vc_toggle title=”SystemVerilog for Advanced Verification”]

• Classes : Object Oriented Programming
• Arrays, Data Types, Literals, Operators
• Scheduling Semantics, Inter process Synchronization
• Processes, Threads, Tasks and Functions
• Randomization, Constraints
• Interface, Clocking blocks, Program Block
• Functional Coverage
• Assertion Based Verification
• System Tasks & Functions
• Compiler Directives
• DPI

[/vc_toggle][vc_toggle title=”ASIC Verification Concepts”]

• SoC Verification Concepts
• Module Level Verification
• Constrained Random Verification
• Coverage Driven Verification
• Directed Verification
• Assertion Based Verification

[/vc_toggle][vc_toggle title=”Verification IP Development”]

• • AXI Protocol Concepts : Features, Signals, Timing Diagrams
  • AXI VIP Architecture Development
  • VIP Component Coding
  • AXI Slave model testcase development
  • Testcase debugging

[/vc_toggle][vc_toggle title=”Module(IP) Level Verification Project”]

• Projects executed: Memory Controller (or) Ethernet MAC (or) DMA Controller (or) AXI2OCP Bridge (or) AXI2AHB Bridge (or) AHB2APB (or) USB Core (or) AXI Interconnect (or) AHB Interconnect (or) a project of similar complexity
• Specification analysis
• Verification Plan creation
• Feature & Scenario Listing down
• TB architecture creation
• Building Top level verification environment
• TB component coding and integration
• Sanity test case and environment bring up
• Complete test case coding
• Building regression test suite
• Functional coverage and code coverage analysis

[/vc_toggle][vc_toggle title=”Verification Methodologies: UVM & OVM”]

• AHB Interconnect verifiation project used as reference design to learn UVM & OVM
• AHB Interconnect will be verified from scratch while teaching all aspects of UVM
• UVM/OVM TB Architecture
• UVM Class Library, Macros, Utilities
• UVM Factory, Synchronization, Containers, Policies
• UVM Components, Comparators, Sequences, Sequencers
• Stimulus Modeling, Sequences & Sequencers
• Creating UVCs and Environment
• Simulation Phases
• TLM Overview, Components
• Configuring TB Environment
• Register Layer, Configuration DB & Resource DB
• Connecting multiple UVCs
• Creating TB infrastructure

[/vc_toggle][vc_toggle title=”AHB UVC Development”]

• AHB Protocol : Features, Signals, Timing Diagrams
• AHB UVC Architecture
• AHB UVC Component Coding
• AHB UVC Seqeunce & Test Development

[/vc_toggle][vc_toggle title=”SOC Design and Verification concepts”]

• SOC Architecture overview
• SOC design concepts
• SOC verification concepts
• SOC Components
• SOC use cases
• SOC Testbench architecture
• SOC Test Case coding
• SOC verification differences with module verification

[/vc_toggle][vc_toggle title=”Linux”]

• Shells
• File and directory management
• User administration
• Environment variables
• Commonly used commands
• Shell scripting basics
• SEd and AWK
• Revision management
• Makefiles

[/vc_toggle][vc_toggle title=”PERL/Python Scripting”]

• PERL Interpreter
• Variables
• File management
• Subroutines
• Regular expressions
• Object oriented PERL
• PERL modules

[/vc_toggle][vc_toggle title=”Course Assignments”]

• VIP Developmet for one of OCP/Wishbone/APB/Ethernet Protocols
• Verification of PCIEx Physical Layer LTSSM FSM from scrach
• Functional Verifcation of a complex module
• UVC Development for AXI Protocol
• PCIe LTSSM FSM Verification
• Register Model Development for SPI Core

[/vc_toggle][/vc_tta_section][vc_tta_section title=”Schedule” tab_id=”1541971524428-6b46e3b3-35fe”][vc_column_text]

Course	VLSI Front End Training for Experienced Engineers
Duration	26 weeks
Next Batches	26/Sept
Demo Session	26/Sept (9AM – 1PM)
Course Enrol	27/Sept
Schedule	Both Saturday & Sunday(8:30AM – 4:00PM India time)
	8:30AM – 12PM (Trainer led theory and lab sessions)
	1PM to 4PM (Mentor guided lab & assignment solving sessions)
New batch starts	every 8 weeks
Fee	INR 39000 +GST at 18% (Students based in India) INR 44,000 + GST at 18% (Students based outside India)
Tool	Questasim
Certificate	Issued based on 50% assignment completion as criteria
Admission criteria	Student need to undergo evaluation test based on Verilog Digital Design VLSI Technology and Aptitude
Assignments	40
Trainer	12+ Years exp in RTL design & Functional verification

[/vc_column_text][/vc_tta_section][vc_tta_section title=”FAQs” tab_id=”1541971537543-694723e5-e96c”][vc_toggle title=”What are the Course Prerequisites?”]

• Expertise on Verilog
• Exposure to Testbench component coding using Verilog

[/vc_toggle][vc_toggle title=”Does course cover practical sessions on SystemVerilog usage?”]

• Each aspect of course is supported by lot of practical examples
• Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
• All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
• Dedicated full day lab sessions to ensure student does complete testbench development from scratch

[/vc_toggle][vc_toggle title=”Is it possible to cover so many things in 8 weeks?”]

• We have done it for 23 Batches so far, next batch is no exception
• Course requires student to spend at least 6+ hours of time a week to revise the concepts

[/vc_toggle][vc_toggle title=”What if I miss few sessions during course?”]Each session of course is recorded, missed session videos will be shared[/vc_toggle][vc_toggle title=”Course has started few weeks back, can I still join the course in between?”]

• Yes, You will have option to view the recorded videos of course for the sessions missed
• You will have option to repeat the course any time in next 1 year

[/vc_toggle][vc_toggle title=”Do you offer support after course completion?”]

• Yes, Course fee also includes support for doubt clarification sessions even after course completion
• You have option to mail you queries
• Option to meet in person to clarify doubts

[/vc_toggle][/vc_tta_section][vc_tta_section title=”Course Material” tab_id=”1541971554383-81d340d2-c773″][vc_column_text]Course Material Shared:

• • SV quick notes, IEEE manual
  • SV Checklist
  • SV Lab Examples
  • AXI VIP Code
  • Ethernet loopback design Testbench Code
  • Memory controller testbench code

 

• UVM User Guide
• UVM Checklist
• UVM Lab Examples
• AHB UVC Code
• AHB Interconnect Testbench Code
• SPI Register Layer code
• USB2.0 Core testbench Code

[/vc_column_text][/vc_tta_section][vc_tta_section title=”Audience” tab_id=”1541971568196-9d55b526-d7f4″][vc_column_text]Target Audience:

• MTech & BTech freshers planning to make career in VLSI Front end domain
• Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
• Engineering college faculty looking to enhance their VLSI skill set

[/vc_column_text][/vc_tta_section][vc_tta_section title=”Trainer” tab_id=”1541971578765-2d5e1f33-6419″][vc_column_text]Trainer Profile

• 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
• Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
• Experience of working on multiple complex module level projects

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