[vc_row][vc_column][vc_tta_tabs style=”modern” active_section=”1″][vc_tta_section title=”Overview” tab_id=”1541971500613-0ec4fc59-2bfc”][vc_column_text]VLSI Online course in Functional Verification (VG-VTO) is a 26 weeks course structured to enable engineers develop expertise in all the aspects of functional verification including ASIC flow, Advanced digital design, STA, CMOS, Verilog, Systemverilog, UVM, Linux OS, PERL/Python scripting, SOC Design and verification and revision management. Online VLSI course is custom designed for online student requirements with theory and lab session timings specifically scheduled at convenient timings. Students are also provided with access to recorded videos for quick revision.

Course includes 9 hands on projects based on Verilog, Systemverilog and UVM, which provides participant with deep insight in to VLSI design and verification aspects. Every aspect of course is supported with detailed examples helps participant with better understanding. Course also covers multiple industry standard projects based on AXI, AHB and Memory Controller. All projects are executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VG-VTO.

[/vc_column_text][/vc_tta_section][vc_tta_section title=”Syllabus” tab_id=”1541971500620-de7bef0f-b03a”][vc_toggle title=”ASIC Flow”]

[/vc_toggle][vc_toggle title=”Advanced Digital Design”]

[/vc_toggle][vc_toggle title=”Verilog for Design and verification”]

[/vc_toggle][vc_toggle title=”SystemVerilog for Advanced Verification”]

[/vc_toggle][vc_toggle title=”ASIC Verification Concepts”]

[/vc_toggle][vc_toggle title=”Verification IP Development”]

[/vc_toggle][vc_toggle title=”Module(IP) Level Verification Project”]

[/vc_toggle][vc_toggle title=”Verification Methodologies: UVM & OVM”]

[/vc_toggle][vc_toggle title=”AHB UVC Development”]

[/vc_toggle][vc_toggle title=”SOC Design and Verification concepts”]

[/vc_toggle][vc_toggle title=”Linux”]

[/vc_toggle][vc_toggle title=”PERL/Python Scripting”]

[/vc_toggle][vc_toggle title=”Course Assignments”]

[/vc_toggle][/vc_tta_section][vc_tta_section title=”Schedule” tab_id=”1541971524428-6b46e3b3-35fe”][vc_column_text]

Course VLSI Front End Training for Experienced Engineers
Duration 26 weeks
Next Batches 26/Sept
Demo Session 26/Sept (9AM – 1PM)
Course Enrol 27/Sept
Schedule Both Saturday & Sunday(8:30AM – 4:00PM India time)
8:30AM – 12PM (Trainer led theory and lab sessions)
1PM to 4PM (Mentor guided lab & assignment solving sessions)
New batch starts every 8 weeks
Fee INR 39000 +GST at 18% (Students based in India)

INR 44,000 + GST at 18% (Students based outside India)

Tool Questasim
Certificate Issued based on 50% assignment completion as criteria
Admission criteria Student need to undergo evaluation test based on Verilog Digital Design VLSI Technology and Aptitude
Assignments 40
Trainer 12+ Years exp in RTL design & Functional verification

[/vc_column_text][/vc_tta_section][vc_tta_section title=”FAQs” tab_id=”1541971537543-694723e5-e96c”][vc_toggle title=”What are the Course Prerequisites?”]

[/vc_toggle][vc_toggle title=”Does course cover practical sessions on SystemVerilog usage?”]

[/vc_toggle][vc_toggle title=”Is it possible to cover so many things in 8 weeks?”]

[/vc_toggle][vc_toggle title=”What if I miss few sessions during course?”]Each session of course is recorded, missed session videos will be shared[/vc_toggle][vc_toggle title=”Course has started few weeks back, can I still join the course in between?”]

[/vc_toggle][vc_toggle title=”Do you offer support after course completion?”]

[/vc_toggle][/vc_tta_section][vc_tta_section title=”Course Material” tab_id=”1541971554383-81d340d2-c773″][vc_column_text]Course Material Shared:


[/vc_column_text][/vc_tta_section][vc_tta_section title=”Audience” tab_id=”1541971568196-9d55b526-d7f4″][vc_column_text]Target Audience:

[/vc_column_text][/vc_tta_section][vc_tta_section title=”Trainer” tab_id=”1541971578765-2d5e1f33-6419″][vc_column_text]Trainer Profile


Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.

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