Online course in UVM & OVM for Functional Verification (VT-VMO) is structured to enable engineers develop their skills in full breadth of UVM & OVM features in complex testbench development. VT-VMO course is targeted for verification engineers who are proficient with SV based functional verification and are looking to explore UVM & OVM based verification. Course has been framed in a way to make UVM & OVM learning a fun and interesting activity. Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple industry standard projects, all of these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VMO.

• UVM & OVM Base class and Macro usage with detailed examples on each construct usage
• AHB Protocol, AHB UVC development & AHB I/C functional verification
• Register layer development for USB2.0
• USB2.0 Core Functional verification

Course Material Shared:

• UVM User Guide
• UVM Checklist
• UVM Lab Examples
• AHB UVC Code
• AHB Interconnect Testbench Code
• SPI Register Layer code
• USB2.0 Core testbench Code

Trainer Profile

• 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
• Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
• Experience of working on multiple complex module level projects