Course Overview
Syllabus
Projects
Schedule
FAQs
Course Material
Certificate
Trainer
Demo
Course Overview
Course Overview
Verilog for Design & Verification (VG-VERILOG) is a 8 weeks course with detailed emphasis on Verilog for complex design implementation and verification. VT-VERILOG course is targeted for both design & verification engineers to gain expertise in Verilog for design & testbench development. This is must do course for every electronics and electrical graduate.
Student may also opt for course on advanced digital design and basic analog design concepts Advanced Digital Design Training .
Course has been framed in a way to make Verilog learning a fun and interesting activity. Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple design implementation examples and testbench setup for the same, and all these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VERILOG
- Verilog language constructs with detailed examples on each construct usage
- Multiple Design Coding & Testbench development
- Access to Questasim tool
- Hands on labs & Hands on projects
- Basic Digital Design Concepts
- Advanced Digital Design Concepts
- Basic Analog Design Concepts
Syllabus
- Verilog language basics
- Verilog : How the language evolved?
- Verilog execution using Modelsim
- Verilog constructs
- Literals
- Data types
- registers, nets
- Vectors, Array
- Operators
- Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
- Continuous assignments
- Combinational logic coding : Half adder, full adder, multiplexer, comparator, encoder, decoder, priority encoder
- Generate
- Procedural timing controls
- task and functions
- system task and function
- modeling memories and FSM
- Parameters
- Port connections
- Procedural blocks
- Sensitivity list
- State machines
- timescale
- Verilog timing regions
- process
- Blocking and nonblocking statements
- Inferring combinational and Sequential logic
- Clock generation with Duty cycle & Jitter
- Shift register implementation
- Procedural Blocks
- fork join
- Race conditions
- Synthesis examples
- Inter and Intra delay statements
- example to showcase race condition using blocking assignments
- Pipelining
- Memories
- Structural modeling
- Verilog Programming Interface(& PLI)
- PLI
- compiler directives
- system task usage: $display, $monitor, $strobe
- PLI, VPI implementation
- Primitive implementation using table, endtable
- DFF coding using gate level, behavioral
- Counters
- Up counter
- Ring counter
- Johnson counter
- Memory RTL coding and TB development
- Memory Verilog coding
- Declaring a parameterized memory
- Front door access
- Back door access test case coding
- Implemneting task for front door and back door access
- Test case coding and understanding waveforms
- FIFO – Synchronous FIFO and Asynchronous FIFO
- Synchronous FIFO
- Asynchronous FIFO
- Finite state machines
- Mealy and Moore style
- Implicit and Explicit styles of coding.
- Pattern detector – Overlapping, Non-Overlapping, Dynamic
- Overlapping
- Non-Overlapping
- Dynamic
- Traffic light controller
- APB protocol
- Interrupt controller
- SPI controller
- CRC generation
Projects
Below is list of projects done as part of Verilog course. All these projects will be done in the live training sessions. All the codes will be done from scratch. There will be lab sessions where student will be doing the same with trainer guidance.
FIFO is a design component used for interfacing data transfer between two components either working on same frequency or a different frequencies. The design was implemented in such a way that there are no race or glitch conditions arise due to design working in two different clock domains. I have implemented both Synchronous FIFO and Asynchronous FIFO using Verilog and the RTL code also verified using Verilog.
SPI Controller is design block that acts as an interface between processor and SPI slaves. SPI architecture is based on one master and multiple slaves. SPI controller has 2 interfaces, one is APB interface used for configuring the SPI registers, address and data, other is SPI interface used for connecting with SPI slaves. SPI uses SCLK, MOSI, MISO and CS to connect master to slave. I was responsible for developing SPI Controller RTL code and verification of the same using Verilog.
Responsibilities
- Listing down design features
- Setting up Testbench and testbench development
- Testcase coding
- Debug the testcases and analyse the waveforms
Interrupt controller is a design used to collect interrupts from various peripheral controllers and forwards the interrupts to processor on priority basis. This continues till all interrupts are serviced by processor. It interfaces with processor on one side using APB interface and another side with peripheral controller. Interrupt controller has configuration registers for programming the various peripheral priority levels, interrupt are processed based on these values. I was responsible for the complete functional verification flow starting from specification reading till verification closure. Testbench environment implemented using SV.
I2C Controller is a design block used for interfacing with I2C master with multiple I2C slaves. I2C controller has 2 interfaces, one is APB interface used for configuring the I2C registers, another is I2C interface using for connecting with I2C slaves. I2C uses SCL and SDA ports for interfacing master to slave. I was responsible for complete verification flow.
PISO(Parallel In Serial Out) and SIPO (Serial In Parallel Out) are required for Serialising and De-serialising data at PHY interface. These has two interfaces for data driving from parallel interface on one side to serial interface on another side and vice versa. It collects the serial incoming data and pushes in to shift register and drives it out to upper layers as a parallel data. It collects parallel incoming data from upper layers and drives it on serial interface. Design also includes buffer to achieve non-blocking data transfers in both transmit and receive paths.
Responsibilities
- RTL Coding for both transmit and receive paths
- RTL integration
- Setting up Testbench and testbench component coding.
- Testplan development
- Testcase coding
- RTL coding and verification of Dynamic pattern detector
- RTL coding and verification of Watchdog timer
- RTL coding and verification of memory wrapper
- RTL coding and verification of Dual port RAM
Schedule
| Course | Verilog for Design & Functional Verification | |
|---|---|---|
| Duration | 8 weeks | |
| Next Batch | 4/March | |
| Schedule | ||
| Freshers | Full week course | |
| Saturday & Sunday(9AM – 5PM India time. Monday to Friday(9:30AM to 12:30PM). Flexible lab sessions for US Students. | ||
| Weekdays sessions will be focused on labs, course assignments, Digital design and interview focused sessions. | ||
| Students also get support on complete project flow during weekdays as well. | ||
| New batch starts | Every 8 Weeks | |
| Tool | Questasim & VCS | |
| Mode of training | Classroom training & Online training | |
| Online training using live training sessions | ||
| Certificate | Issued based on 50% assignment completion as criteria | |
| Batch Size | 20 | |
| Assignments | 16 | |
| Trainer | 12+ Years exp in RTL design & Functional verification |
FAQs
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
No per-requisites. Good to know C language & exposure to Digital Design concepts
- Each aspect of course is supported by lot of practical examples
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Course Material
Below course material is shared as part of the course. All these are done as part of the regular sessions.
| Verilog Material | Access | |
|---|---|---|
| Course material | Shared over google drive consists of IEEE Manual-Labs & project code | |
| Course page access | Get login details from Admin | |
| Assignments-Checklist-Session notes | Course page | |
| Labs | Shared as part of course material and also shared every week | |
| Gvim install & usage | Youtube video shared as part of course guidelines | |
| How to use course material | Share as part of Course material | |
| Resume update | Share as part of Course material | |
| Session Notes | Uploaded to the course page | |
| Interview Questions | Uploaded to course page | |
| Labs for every week session | sent as mail attachment at the end of every week |
| Students enrolled for the course(Log in to youtube using gmail Id to view below videos): |
|---|
| Click here to view Course Page access video |
| Click here to view Questasim usage video |
| Click here to view VCS Usage video |
| Click here to view GVIM editor video |
Student will get access to assignments, labs, session notes, interview questions, sample resumes on course page.
Certificate
Trainer
Experienced Trainer
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
Demo
Play Video
- 1-1 Dedicated Mentor Support
- 24/7 Tool Access
- Multiple MOCK Interviews
- Industry Standard Projects
- Resume Preparation