SESSION#1 (28/March)


– SOC consists of various types of components
o Processors, INTC, Interconnect, PMU, DMA, Bridge, Peripheral controllers
o Peripheral controllers
o UART controller, SPI controller, I2C controller, USB controller, PCIe controller, DDR controller, SDIO controller, Memory controller
– controller acts as an interface between processor(s) and actual peripheral(ex: Pendrive, MMC card, KBD, Mouse, etc)
– Why we need USB controller?
o Open laptop, 100MB movie file, we want to transfer to Pendrive
o 100MB file is present in my laptop harddisk
o Harddisk itself can’t initiate the transfer, hence processor comes in to picture
o Laptop SOC has a component called DMA (Direct Memory Access)
o Processor programs DMA to read data from Harddisk
o processor is delegating the transfer work to DMA, during this time processor is free, it can address some otehr component
o Processor programs DMA to give the data to USB2.0 controller
o why controller is required? why can’t we directly give data to pendrive?
o processor, DMA controller, harddisk are all sitting on AXI interconnect
o their all transactions will be interms of AXI protocol only(not in the USB frame format)
o this is where we need USB2.0 controller
o which will take transactions in AXI format and convert these transactions in to USB frame format.
o DMA controller will generate AXI transactions to USB controllers
o USB controller will understand incoming AXI tx, converts it in to USB Frame format
o frame in turn consist of SOF packet, token packet, Data packet, HS packet, Special packets
o If target device is USB3.0 device => controller is USB3.0 controller
o If target device is USB2.0 device => controller is USB2.0 controller
– what will happen if we don’t have controllers?
o all the complexity will go in to processor/DMA
o processor will have to generate USB frame(SOF, token, Data, HS, etc)
o processor has to detect when the pen drive is connected, what is type of pen drive
o Processor is delegating all the USB communication related activities to USB controller, it is only giving top level instrucitons to the USB controller
o USB controller will generate USB frame
o USB controller will detect when pen drive is connected
o USB controller will detect the type of devivce connected
o Processor will only give top level instructions to USB controller
o USB controller has control and status registers
o Processor pgroams control registers to indicate what is the kind of behavior it wants.

SPI Controller:
– acts as an interface between processor and SPI Slave device
DDR3 controller:
– acts as an interface between processor and DDR3 memory
Universal memory controller:
– acts as an interface between processor and various types of memories(dram, sram, flash, rom, scsd, etc)
– without Universal memories controller, processor will get very compilcated, it will have to handle all memory related features
o refresh : self, auto
o oepning bank
o row activation
o precharge
o burst transafers
o sram
o flash
– UMC has 19 registers
o processor will program these 19 registers to tell UMC on how it should behave
o ex: when to issue refresh, when to do burst, what is lenght of burst

  1. Different types of storage (for each, benefits, drawbacks)
    • Flipflop
      o quick in access
      o takes higher footprint(~more transastors to implement)
    • sram
      o cross coupled inverters: both of them creating a feedback mechasism, which makes it attain the final value very quickly => quick in access
      o Drawback: more transastors are required
    • sdram
      o 1 transistor + 1 capacitor(~parasitic)
      o word line, bit line
      o word line is to activate group of transistors
      o bit line carries the data to write or read
      o SDRAM cell value is stored in to the capacitor
      o Value is accessed by sensing this capacitor (sending capacitor charge)
      o Value is written by transfering charge from Bit line to capacitor
    • flash
  2. Memories are 2 types
    o volatile
    o once power is turned off, data is lost (ex: sram, sdram, etc)
    o non-volatile
    o once power is turned off, data is still stored(ex: flash, sdcard, MMC card, harddisk, ROM)
  3. SDRAM
    o x4 SDRAM
    o each row, colum combination has 4 SDRAM cells
    o when we perofmr read to a row & colum, we get 4 bits of data
    o x16 SDRAM
    o each row, colum combination has 16 SDRAM cells
    o when we perofmr read to a row & colum, we get 16 bits of data
  4. SDRAM memory organization
    o SDRAM
    o Ranks
    o Single, Dual rank
    o Each rank consist of multiple SDRAM memories
    o Each SDRAM memory consist of multiple banks
    o Each bank consist of multiple rows and columns (matrix)
    o Each row and column combination consists of multiple SDRAM cells(this count is what is xn sdram)
    o SDRAM are accessed with either 32 bit data interface or 64 bit data interface
    o when user peforms a read(64 bit data read) => when we pefrom read, sDRAM should return 64 bits of data
    o assume that we are using X8 SDRAM => how can it return 64 bits of data?
    – connect 8 SDRAM’s (8X8 = 64 bits of data) => one RANK
    o Keeping togehter 2 such sets of SDRAM => Dual RANK memory
  5. SDRAMs are inherently slower in access, since their values are stored in to capacitors, capacitors access is slow
    o SDRAM access is slower
    o SOlution: we use Sense Amplifiers for each Bank
  6. SDRAM supports only burst lenght of 2, 4, 8, 16 lenght bursts
    o if we want to do burst transfers of length 5
    o we start with burst lenght of 8, once 5 transfers are done, terminate the transaction. This is called burst terminate
  7. Flash
    o charge is stored inside MOSFET between Gate and Substrate
  8. SDRAM
    o Mmeory controller is connected to SDRAM
    o we activiated a row
    o ROw content is being copied from SDRAM cells to Sense amplifiers (in real life it takes some time) => during this time we should not to any other operation(like write/read, burst terminate, etc)
    o Memory controlelr should know these delay values
    o if we precharged a row(copying back contents from SA to SDRAM cells), during this time we should not do any other operation.
  9. while refresh is in progress, we can’t perform any write-reads, we can’t do any otehr operations
    o hence we divide the memory in Banks
    o while one bank is refreshed, otehr bank can’t written/read => this reduces dependency
  10. Each memory has different value of activate time, precharge time, write/read time, burst terminate time,
    o memory controller needs to programmed diffeently for each of these values
    o memory controller has TMS(timing mode slection) registers where we can program different values of activate, precharge, write/read, etc
  11. Why TMS reigsters are required in Memory controller?
    o why 8 TMS registers are required?
    o TMS registers holds the different timing values specific to each chip select
    o Since 8 CS’s are there, 8 TMS regisers are required
  12. Burst transfer?
    o Using minimal time to do maximum number of transfers
    o one address phase, multiple data phases
    o brust transfer of 16 length
    o address is issued only once, data is trasnferred 16 times
    o Overall 17 clock cycles, we did 16 data transfers
    o what if burst transfer not supported?
    o for 16 data transfers => ti will take 32 clock cycles
  13. Burst terminate
    o we start with burst lenght of 8, once 5 transfers are done, terminate the transaction. This is called burst terminate
    o MC does not support all burst lenght
  14. RMW
    o Read Modify and write
    o MC reads a location, modifies the contents, write back to memory
  15. Performance optimization by leaving active rows open
    • If we are accessing 1024 Words of data
      o most of the times, these access will be to continuous locations
      o mostly they will be belonging to same row, continuous columns
      o if we go by normal practice:
      o activate a row, read a column, get the data, precharge the row
      o activate same row, read the next column, get the data, precharge the row
      o activate same row, read the next column, get the data, precharge the row
      so on
      o lot of time will be lost in precharging the same row and activating the same row agian and again
      o Memory controller has a register with field called KRO (Keep row open) => once the row is accessed, keep the row open(don’t precharge it)
      o this will help avoid unncessary time loss in prechrage and reactivation
  16. Default boot sequence support
    Lets take mobile phone
    o when we turn on phone, processor has to boot up
    o boot happens using a image(binary data), this image is present in one of the memories
    o this memory is also accessed using a memory controller
    o processor is not yet up => memory controller is not yet programmed(configured) => how can we access the memory => without accessing memory, we can’t read memory boot image => unless processor reads boot image, it will not boot up => Catch22 situlation
  1. Byte parity Generation and Checking
  1. Memory controller sub blocks
    o configuation and status registers
    o all the registers required for MC operation
    o processor programs these registers to configure the memory controller functionality
    o SDRAM memory internally has a register called as MODE register
    o when we pefrom a write to TMS register(if the correspnding memory is SDRAM) => MCTRL inturn generates write to Mode register => mode register decide the SDRAM behavior
    o wishbone interface
    – interface between system(processor) and memory controller
    – it understand the incoming WB transaction and gives furhter signaling to rest of MC logic
    – decode the WB transactions from processor
    o power down controller
    o Open bank & row tracking
    o for all teh chip select with SDRAM connected, it will keep track of which Bank and row is currently open
    KRO : Keep Row Open
    o this is applicable only when KRO=1
    o what if KRO=0 => this block has no singinface? => KRO=0 => we are telling that close the row(precharge the row) as soon as access is done, hence there is no concept of row being opened at all => there is no need to track of Open Bank and Row
    o Refresh controller
    o MC supports connecting up to 8 memories
    o lets say, we connected 5 among them to be SDRAM
    o each SDRAM may have different refresh interval(minimum time during which refresh must be done, else we can’t gaurantee the data holding in SDRAM)
    o we need to refersh all SDRAM, for this purpose we will use the smallest refresh interval among all teh connected SDRAM
    ex: SDRAM#CS0 (RI : 5ns), SDRAM#CS1 (RI# 9ns), CS2 (11ns), CS3 (4ns), CS4 (15ns)
    o what is the refresh interval? 4ns
    o while one bank is refreshed, we can still write/read to otehr banks in SAME MEMORY.
    O REFRESH controller figures out these values, gets the lowest among these, issues refresh once every 4ns, so that all SDRAMs gets refreshed.
    o Power on configuation
    o When the system is booted up, from which memroy processor should start fetching the image
    o this data will be stored in to POC register => this register will tell which memory to be booted from
    o Memory timing controller
    o Takes care of timing during memory transactions
    o ex: if refresh is issued, when to issue activate, this delay is implemented by timing controller(it gets inputs from configuration registers)
    o ex: if row activation is issued, when to issue write/read, this delay is implemented by timing controller(it gets inputs from configuration registers)
    o address multiplexer and counter
    o Memory controller has various types of memories connected on different chip selects
    o Memory controller generates all the address for different memories
    o address multiplexer is responsible for figuring out the type of memory connected and choosing that address using MUX
    o data latch, packer and parity
    o latch: latchng the data at memory interface
    o packer: packing the collected data in 32 bit bus
    o parity : generating parity bits based on type of pairty during memory writes
    o also for parity checking on memory reads
    o memory interface
  2. Memory controller operation/features
  3. Chip Select
    o memory controller has 8 regiser, one for each chip select
    o BA_MASK register
    o 8 memories connected, we need below information
    o if Wishbone target address(wb_addr) is falling inside {[CS2_START_ADDR:CS2_END_ADDR]}
    o then CS2 is selected
    o Memory controller has a register called CSC2 (Chip select configuration register 2)
    CSC2 = 32’h12345678;
    = 32’b0001_0010_0011_0100_0101_0110_0111_1000 for memory connected to Chip Select#2, following things apply o CSC2.Sel = 8'h34 o CSC2.PEN = 0 (for memory connected to CS2, do not generate parity or do not do parity checking) o CSC2.KRO = 1 (for CS2 connected memory, if it is SDRAM, keep the row open after the accessing is completed, close the row only when new row needs to be opened) o CSC2.BAS = 1 (how to decode the incoming Wishbone address in to Bank address, row address, and column address) o WB_ADDR[31:0] = {Bank_address, row_address, column_address} o if BAS=0 => WB_ADDR[31:0] = {row_address, Bank_address, column_address} o CSC2.WP = 0 => We can pefrom writes to memory connected on CS#2 o CSC2.MEM_SIZE = 2'b01 => 128Mbit memory is connected to CS#2 o CSC2.BW = 2'b11 => Reserved Bus width => WRONG PROGRAMMING o CSC2.MEM_TYPE = 3'b100 => Reserved MEM_TYPE => WRONG PROGRAMMING o CSC2.EN = 1'b0 => Chip select is disabled (We can't access this chip select) CSC2 = 32'h12345678; ==> DO We get this value randomly => NO We have to come up with this manually based on what we want to conenct at CS#2Lets say, we want to connect 64Mbit SDRAM, 32 bit BW to CS#3, what should we program in CSC3 register? CSC3 = {8'h0, 8'b0000_1000, 4'b0, 1'b1, 1'b1, 1'b0, 1'b0, 2'b0, 2'b10, 3'b0, 1'b1} = 32'h0008_0C21} We will program 32'h0008_0C21 value in to CSC3 register </code></pre></li>

When Processor generates a WB transaction targeting address in the range of {[CS3_START_ADDR:CS3_END_ADDR]}
o CSC3.SEL & BA_MASK, it will be checked against wb_addr[28:21] => if this matches, CS3 is being targeted
o without this concept of BA_MASK, we will need 16 registers for CS0/1/2/3/4/5/6/7 START, END => 16 registers

  1. Memory mapping
    1st approch:
  2. CS range calculation
    BA_MASK = 8’b1111_1111;
    CSC0.SEL = 8’b0000_0001
    CSC1.SEL = 8’b0000_0010
    CSC2.SEL = 8’b0000_0100
    CSC3.SEL = 8’b0000_1000
    CSC4.SEL = 8’b0001_0000
    CSC5.SEL = 8’b0010_0000
    CSC6.SEL = 8’b0100_0000
    CSC7.SEL = 8’b1000_0000

Based on above lets calculate the range of CS0
BA_MASK & CSCn.SEL == wb_addr[28:21] => CSn is targeted in this Wishbone transaction
8’b1111_1111 & CSC0.SEL
8’b1111_1111 & 8’b0000_0001 => wb_addr[28:21] should match this
wb_addr[28:21] = 8’b0000_0001
wb_addr[31:29] = 3’b000 => We will understand this when we MEM_CTRL Spec
lowest address in the range is when we keep wb_addr[20:0] as all 0’s
highest address in the range is when we keep wb_addr[20:0] as all 1’s

    CS0 STARTING ADDRESS = {3'b000, 8'b0000_0001, 21'h000000}
    CS0 STARTING ADDRESS = {32'b000_0000_0001_0_0000_0000_0000_0000_0000}
    CS0 STARTING ADDRESS = {32'b0000_0000_0010_0000_0000_0000_0000_0000}
    CS0 STARTING ADDRESS = {32'h0020_0000}

    CS0 END ADDRESS = {3'b000, 8'b0000_0001, 21'h1FFFFF}
    CS0 END ADDRESS = {32'b0000_0000_0011_1111_1111_1111_1111_1111}
    CS0 END ADDRESS = {32'h003F_FFFF}
    If BA_MASK = 8'hFF, CSC0.SEL=8'h01 => CS0 ADDress range is {[32'h0020_0000:32'h003F_FFFF]}

8’b1111_1111 & CSC0.SEL
8’b1111_1111 & 8’b0000_0010 => wb_addr[28:21] should match this
wb_addr[28:21] = 8’b0000_0010
wb_addr[31:29] = 3’b000 => We will understand this when we MEM_CTRL Spec
lowest address in the range is when we keep wb_addr[20:0] as all 0’s
highest address in the range is when we keep wb_addr[20:0] as all 1’s
CS1 STARTING ADDRESS = {32’b0000_0000_0100_0000_0000_0000_0000_0000}
CS1 STARTING ADDRESS = {32’h0040_0000}
CS1 END ADDRESS = {32’b0000_0000_0101_1111_1111_1111_1111_1111}
If BA_MASK = 8’hFF, CSC1.SEL=8’h02 => CS1 ADDress range is {[32’h0040_0000:32’h005F_FFFF]}

CS#2: If BA_MASK = 8’hFF, CSC2.SEL=8’h04 => CS2 ADDress range is {[32’h0080_0000:32’h009F_FFFF]}
CS#3: If BA_MASK = 8’hFF, CSC3.SEL=8’h08 => CS3 ADDress range is {[32’h0100_0000:32’h011F_FFFF]}
CS#4: If BA_MASK = 8’hFF, CSC4.SEL=8’h10 => CS4 ADDress range is {[32’h0200_0000:32’h021F_FFFF]}
CS#5: If BA_MASK = 8’hFF, CSC5.SEL=8’h20 => CS5 ADDress range is {[32’h0400_0000:32’h041F_FFFF]}
CS#6: If BA_MASK = 8’hFF, CSC6.SEL=8’h40 => CS6 ADDress range is {[32’h0800_0000:32’h081F_FFFF]}
CS#7: If BA_MASK = 8’hFF, CSC7.SEL=8’h80 => CS7 ADDress range is {[32’h1000_0000:32’h101F_FFFF]}

if processor generates a write to 32’h0200_0300
which Chip select is targeted? CS#4 will be selected (this is our calculation)
what memory controller will do?
wb_addr[28:21] = 8’h20
ba_mask = 8’hFF, it will take all CSCn.SEL, does bitwise ANDing
o whichever matches, that CS is target
o 8’hFF & CSC4.SEL = 8’hFF & 8’h20 => THIS is matching with wb_addr[28:21] => hence 32’h0200_0300 is targeting CS#4.
o CS#4 is selected, memory controller will fetch the values of CSC4 & TMS4 registers
o from these registers it will figure out followign
o timing parameters from TMS registers
o according to above parameters MEM_CTRL will work(only for current wishbone operation)

if processor generates a write to 32’h0040_0120
which CS is targeted? CS#1
BA_MASK & CSCn.SEL == wb_addr[28:21] = 8’h04 => this matches of CS#1
o CS#1 is selected, memory controller will fetch the values of CSC4 & TMS4 registers
o from these registers it will figure out followign
o timing parameters from TMS registers
o according to above parameters MEM_CTRL will work(only for current wishbone operation)

BASELINE: we don’t have 16 different registers for hdoling address range values.

if processor generates a write to 32’h0440_0100
ba_mask & cscn.sel == 8’h44 => it does not match for any of the chip selects
hence this will result in decode error

SESSION#2 (29/March)


  1. byte parity generation total there will be 32 +4=36 bits, how can we send 36 bits in a 32 bit data bus?
    • data bus width will be 36 including parity bits


  1. Memory controller has 2 interface
    o Host interface: implementing using wishbone protocol(it could have been AXI, AHB, APB, any protocol)
    o Processor(s) connect to MEM_CTRL using this interface
    o Processor can access 2 things
    o MEM_CTRL registers
    o 19 registers
    o CSC0-7, TMS0-7
    o 8 different/similar memories can be connected to the MEM_CTRL, each can have different timing parameters
    o what is different timing parameters means?
    o SDRAM connected CS#0 may only require 5ns for activate a row
    o SDRAM connected CS#1 may only require 7ns for activate a row
    o FLASH connected CS#2 may have some otehr timing requiement
    MEM_CTRL should be aware of all these parameters correspnding to each memory connected on different chip selects.
    These timing parameters are programmed in to TMS register(32 bit)
    sicne timing parameters are different for each Chip select, we need 8 TMS registers.
    o Why we need CSC0-7?
    o each Chip Select can have diffrent memories connected, with different size, bus width, KRO, memory type, etc
    o Memories connected to the MEM_CTRL
    o Memory interface : it is used for connecting different types of memories(sram, sdram, flash, rom, scsd)
  2. wb_addr[31:29] == 3’b000 => Memories are being targeted
    wb_addr[31:29] == 3’b011 => Registers are being targeted
    what if different vlaue?
    o Decode error, we are targeting a non existant location
  3. Chip Select
    o concept where MEM CTRL figures out which memory chip is being targeted by current Wishbone address
    o memory controller has 8 regiser, one for each chip select
  4. Calculating the Chip Select address ranges
    o User should program BA_MASK, Selection values for each of the Chip select
    BA_MASK = 8’b1111_1111;
    CSC0.SEL = 8’b0000_0001
    CSC1.SEL = 8’b0000_0010
    CSC2.SEL = 8’b0000_0100
    CSC3.SEL = 8’b0000_1000
    CSC4.SEL = 8’b0001_0000
    CSC5.SEL = 8’b0010_0000
    CSC6.SEL = 8’b0100_0000
    CSC7.SEL = 8’b1000_0000
    – all these SEL values should be unique. for a wb_addr to target CS0 => ba_mask & CSC0.SEL == wb_addr[28:21] => if this is true, then wb-addr is for CS#0
    what is the range of wb_addr which will meet above requirement?
    – wb_addr[31:29] = 3’b000
    – wb_addr[28:21] = 8’b0000_0001
    – wb_addr[20:0] = THIS IS THE FLEXIBILITY USER HAS
    Ex: If Karnataka Pin code start 515, Pincode has 6 digits, what is lowest PIN code in Karnataka = 515000
    what is the highest pin code = 515999 what is the lowest WB_ADDR that can target CS#0: {3'b000, 8'b0000_0001, 21'b0_0000_0000_0000_0000_0000} CS0 STARTING ADDRESS = {32'h0020_0000} what is the highest WB_ADDR that can target CS#0: {3'b000, 8'b0000_0001, 21'b1_1111_1111_1111_1111_1111} CS0 END ADDRESS = {32'h003F_FFFF} Conclusion:
    o analogy: you send any post with pincode between 515000 to 515999, it will compolsorily go to Karnataka.
    o If wb_addr is targered between {32’h0020_0000:32’h003F_FFFF}, transaction will go to CS#0
    o we don’t know what is conencted to CS#0
    o HOW DO WE GET ALL THE INFORMATION about memory connected to CS#0?
    o CSC0, TMS0 registers o CS#1 address ragne
    for a wb_addr to target CS1 => ba_mask & CSC1.SEL == wb_addr[28:21] => if this is true, then wb-addr is for CS#1
    8’b1111_1111 & 8’b0000_0010 = 8’b0000_0010 (this should be wb_addr[28:21])
    what is the lowest WB_ADDR that can target CS#1: {3’b000, 8’b0000_0010, 21’b0_0000_0000_0000_0000_0000}
    CS1 STARTING ADDRESS = {32’h0040_0000}
    what is the highest WB_ADDR that can target CS#1: {3’b000, 8’b0000_0010, 21’b1_1111_1111_1111_1111_1111}
    CS1 END ADDRESS = {32’h005F_FFFF} o CS#2 address ragne
    CSC2.SEL = 8’b0000_0100
    NOTE: CS address is not fixed for memory controller, it is function of what is programmed in to BA_MASK and CSC registers
    CS2 = {[32’h0080_0000:32’h009F_FFFF]} o CS#3 address ragne
    CSC3.SEL = 8’b0000_1000
    CS3 = {[32’h0100_0000:32’h011F_FFFF]} o CS#4 address ragne
    CSC4.SEL = 8’b0001_0000
    CS4 = {[32’h0200_0000:32’h021F_FFFF]} o CS#5 address ragne
    CSC5.SEL = 8’b0010_0000
    CS5 = {[32’h0400_0000:32’h041F_FFFF]} o CS#6 address ragne
    CSC6.SEL = 8’b0100_0000
    CS6 = {[32’h0800_0000:32’h081F_FFFF]} o CS#7 address ragne
    CSC7.SEL = 8’b1000_0000
    CS7 = {[32’h1000_0000:32’h101F_FFFF]}

CS#2: If BA_MASK = 8’hFF, CSC2.SEL=8’h04 => CS2 ADDress range is {[32’h0080_0000:32’h009F_FFFF]}
CS#3: If BA_MASK = 8’hFF, CSC3.SEL=8’h08 => CS3 ADDress range is {[32’h0100_0000:32’h011F_FFFF]}
CS#4: If BA_MASK = 8’hFF, CSC4.SEL=8’h10 => CS4 ADDress range is {[32’h0200_0000:32’h021F_FFFF]}
CS#5: If BA_MASK = 8’hFF, CSC5.SEL=8’h20 => CS5 ADDress range is {[32’h0400_0000:32’h041F_FFFF]}
CS#6: If BA_MASK = 8’hFF, CSC6.SEL=8’h40 => CS6 ADDress range is {[32’h0800_0000:32’h081F_FFFF]}
CS#7: If BA_MASK = 8’hFF, CSC7.SEL=8’h80 => CS7 ADDress range is {[32’h1000_0000:32’h101F_FFFF]}
All above calculations(or the address ranges) only based on BA_MASK and Selection values.
o if they get changed, address ranges will change.
o WHO Can change those values? IN the SOC architecture who can change those values?
o processor can program BA_MASK and CSCn.SEL values to come up with new range of mem_ctrl emmory address ranges.

  1. in FLASH memory(Asynchronous Chip Select devices), we don’t connect multiple memories
    o MEM_CTRL does multiple write/reads to add up 32 bits
    o x8 Flash memory
    o MEM_CTRL will issue 4 writes to 4 continous locations to totally write 32 bits of data.
    o MEM_CTRL will issue 4 reads to 4 continous locations to totally reads 32 bits of data.
    o x16 Flash memory
    o MEM_CTRL will issue 2 writes to 2 continous locations to totally write 32 bits of data.
    o MEM_CTRL will issue 2 reads to 2 continous locations to totally reads 32 bits of data.
    o x32 Flash memory
    o MEM_CTRL will issue 1 writes to 1 continous locations to totally write 32 bits of data.
    o MEM_CTRL will issue 1 reads to 1 continous locations to totally reads 32 bits of data.
  2. for all other memories, we connect multiple memories to toally add up BUS WIDTH to 32 bits
  3. 1st phase

module mt48lc2m32b2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
1st phase: (selecting a Bank and a row)
BA will be sent on Ba
Row_addr will be sent on Addr

2nd phase: (Selecting a Bank, open a row)
BA will be sent on Ba
Column_addr will be sent on Addr
I am using Addr to send both Row and COlumn addresses. Hence we are saving number of pins required.

  1. All memories supported in to 4 categories
    o SSRAM
    o SDRAM
    o Asynchornous Chip Select device memory (ACSD) => They don’t have clock at their interface
    o Flash
    o Synchornous Chip Select device memory (SCSD)
    o ROM
  2. SRAM timing diagram: Observations
    • Read tx involves latency, once MEM_CTRL issues read request, there is latency by the time MEM_CTRL gets the data(Tsrdv : Time for SRAM read data valid)
    • address phase is valid, when adsc=0
    • tx is a write tx, when we_ = 0
    • tx is a read tx, when oe_ = 0
    • during write/read, when adv_ = 0 => data access is happening.
    • once the tx completes, adsc, adv, oe, we all should be high
  3. Async memroy
  1. SCSD
    Read tx:

Write tx:

  1. TMS register has polymorphism kind of behavior
    • same TMS register has different meaning based on what type of memory is connected.
    • if SDRAM is connected, TMS has SDRAM speciifc meaning.
  2. addressing happens at byte addressing at wishbone interface
    o each byte has a unique address
    addressing happens at word addressing at memory interface
    o each word has a unique address
  3. wb_addr = 04
    mem_intf.addr = 01 (word to byte conversion involves division with 4)
    16 byte burst => 4 word burst =>
    boundaries: 0-3, 4-7, 8-11, 12-15, so on
    01 falls 0-3 boundary range
    D1, D2, D3, D0
    D1 : Data that is accessed at address location#1
    D2 : Data that is accessed at address location#2
  4. what we understood in MEM_CTRL
    o architecture
    o sub blocks
    o interface
    o protocol used for interface
    o interface ports
    o clocks
    o regsiters
    o features
    o how different features are implemented
    o operations, how they are implemented
    o timing diagrams for different operations
    o suspend, resume
    o external bus master
    o write-read
    o burst transfers
    o wishbone access
    o how individual memories work
    o memory organization
    o concept of chip select
  5. Memory Controller Verification : Steps followed
    • Feature listing down
    • Scenario listing down
    • Test plan development
    • Functional coverage point listing down
    • Testbench architecture definition
    • Testbench component coding
    • Sanity Testcase development
    • Sanity testcase bringup
    • Functional testcase coding
    • Setting up regression
    • Running regression, debugging regression results
    • Generating coverage reports
    • Analyzing coverage reports, developing directed tests
    • Closing functional verification
    • 100% test case pass
    • 100% functional coverage
    • 100% code coverage
  6. 100 people who attending training
    • only 30 people read the spec
    • onle 20 peiple start the project
    • only 10 people manage to complete the project
      do you want to be in 70 people or 30 people or 10 people?



  1. are refresh ,precharge and KRO related to each other?
    • refresh is not related
    • precharge and KRO are related
      o if KRO=1 => precharge will not happen as soon as write/read completes
      o if KRO=0 => precharge will happen as soon as write/read completes
  2. word: 4 bytes
    halfword: 2 bytes
    double word: 8 bytes



  1. testplan
  2. TB architecture
  3. TB component coding
  4. Sanity testcase bringup


  1. testplan
    • testplan will be reviwed by senior members in team.
  2. testbench
  3. functional coverage point listing down
    Essential checks user should have done to say verification is complete. Below read them as ‘did I’ then read the line.
    Write & read to all chip selects
    Burst write, read to all chip selects
    Chip select 0 not active
    Different burst length transfers
    Transfers to different memory types
    Timing parameter configuration for different memories
    RMW access
    MC suspend & resume
    Different error types
    Different configurations of SDRAM, SSRAM, FLASH
    Dynamic bus sizing
    SDRAM access with keeping row open after access, closing row after access
    Turning off flash
    Refresh interval & pre-scalar for SDRAMs
    Parity enable
    Packing of 8 & 16 BW data
    Different address range targeted
    Reset during suspend
    Write & read during suspend
    Different BA_MASK configurations
    All chip selects connected to same memory device
    Accessing different bank in SDRAM with row open after access
    Burst transfers at different starting address locations
    Memory bus arbitration
    Multiple CS configured for same base address
    Accessing memories while turned off

4. Sanity testcases

  1. TB Coding
  1. Unix command
  2. TB Coding
    • template coding
      o basic skeletal structure with no functionality
    • functionality coding
  3. functionality coding
    • from where to start?
  4. register write
    32’h60000030, 32’hd76459f7




  1. Developed MEM_CTRL testplan
    o features, scenarios, testcase, description, detailed flow of test, status, debug-comments
  2. TB architecture
    o components on WB interface
    o generator, bfm, monitor, coverage, assertion
    o components on memory interface
    o monitor
    o slave model : memories
  3. If we are verifying USB controller
    • at bigger level USB controller connects to 2 things:
      • processor, USB device
      • to verify USB controller, we can’t get real processor(physical device), we can’t even connect real pen drive device
        o we rather model their behavior
        o what if processor is tehre? what it will do? assume interface is AXI protocol
        o AXI BFM, generator, monitor, coverage
        o AXI assertions
        o what if USB device is tehre? what it will do?
        o It will get frames from USB controller, it will response some response packets
        o We will model this using USB slave model(which will behave as if there is a USB device present)
  4. In case of memory controller
    o Memory controller on one side connected to processor(s)
    o Memory controller on other side connected to memories
    o memories are called as slave models
    o memories are slaves to the memory controller
    o memroy controller is slave to processor
  5. List sanity testcases
    reg_reset, reg_wr_rd, 4 memory basic access tests
  6. Developed register access tests
    o random order case (testname)
    “test_reg_reset” : begin
  7. Apply reset to design will make all registers take reset values
    o by using this test, we are checking whether registers are INDEED taking the reset values or not
    o we will get reset values from the specification
  8. TB Coding
  1. TB Development
    o template coding
    o skeletal structure of the TB with no functionality coded
    o task run with one display
    o functionality coding
    o where do we start this?
    o generator
  2. testcase development
    o approach#1 : testcase developed in to generator (what we did)
    o approach#2 : testcases are developed in to separate file, include that file, use those testcases in generator
    o there may be approach#3
    o Verificaiton engineer should be flexible to understand any kind of TB strucure
  3. How to develop (very important skillset for a verification engineer)
    o how to create groups
    o signals are stored in to file
    o when we open, saved format signals will open up
    o it saves time in adding the signals, groyping them, etc
  4. how do we bring in random order in to regsiter access?
    Q.push_back, Q.shuffle, mbox.put(Q.pop_front)
  5. Testcases and TB component coding
    sanity testcases
    o test_cs0_sram
    o test_cs0_sdram
    o test_cs0_flash
    o test_cs0_scsd
  6. test_cs0_sram
    o SRAM is connected to CS0
    o configure CSC0 & TMS0 for SRAM specific configuration
    o write and read to CS0(~essentially to SRAM)
  7. testcase will be done in 4 steps
    o reset
    o power up => This is not relevant for MEM_CTRL
    o configuration
    o traffic
  8. if mc_dqm = 4’b0110, mc_dq[31:24] are invalid, mc_dq[23:16] valid, mc_dq[15:8] valid, mc_dq[7:0] : invalid
    mc_dqm indicates which byte positions are valid in mc_dq
  9. mc_dq connections
    //when we write to memory, Dq port acts as input, it should be connected to mc_data_pad_o of memory controller
    //when we read from memory, Dq port acts as output, it should be controller to mc_data_pad_i of memory controller
    //mc_dq should be driven during write operation
    //WRITE Operation: MEM_CTRL should give data on mc_data_pad_o -> it should go to mc_dq, which it turn connected to Dq port of SRAM, hence SRAM will get the write data
    //mc_dq should be floating during read operation
    //Read Operation: MEM_CTRL should get the data on mc_data_pad_i -> it should not give any data on mc_dq(by driving z)
    //SRAM will give data on Dq, which is inturn connected to mc_dq => which will by asigned to mc_data_pad_i => which gives data in to MEM_CTRL
  10. SRAM
  1. Verification engineer
    • expectation is not about reporting the top level issue
      • expectation is to debug the issue, figure out possible causes, find the actual cause, reprot this to the team
      • make the debug simpler
        • currently we are generating 10 tx(10 write, followed by 10 reads)
      • HOW DO WE DEBUG?
        o list down the steps?
        o is the tx reaching memory interface?
        o addr, data ports of mem_intf need to be checked during write
        o during write: sel = 4’ha = 4’b1010 (3rd and 1st bytes should be written, data[23:16], [7:0] are invalid => do not write this to memory)
        dqm = 4’h5 = 4’b0101 (2nd byte and 0th byte are not valid, memory will only accept 1st & 3rd bytes)
        because we are masking those positions
        dqm is active low signal => 0 means valid, 1 means invalid
        o is the CS0 selected?
        mc_cs_pad_o[0] bit as 0 => cs0 is selected
        o is the memory write happening?
        yes. but only 2 bytes are written
        o is the memory read happening?
        when we read, we only get 2 bytes as valid
        o are we getting same data during memory read(whatever we wrote)?
        o is the read data coming to Wishbone interface?
        o memory write did not happen to all the locations
        o why?
        o we generated a random wb_sel value, ehnce only few of data bytes are written
        o SOlution: put constraint on sel == 4’hF
  2. wb_addr = 32’h319340 = 32’h0011_0001_1001_0011_0100_0000
    mem_addr = 20’hc64d0 = 20’h1100_0110_0100_1101_0000
    ignore lower 2 bits of wb_addr(byte to word level conversion) (right shift by 2 bits means division by 4)
    wb_addr = 32’b0011_0001_1001_0011_0100_00 in word addressing
    readjsut with each as 4 bits
    wb_addr = 32’b00_1100_0110_0100_1101_0000 in word addressing
    wb_addr = 32’b0C64D0 in word addressing
  3. Steps involved in creating new test
      o add a new case statement with testname
      o implement all the register programming
      CSC, TMS will change
      o memory write/read will be same
      o only CS ranges need to be updated
      o `include the new memories that are used in current test
      o instantiate and connect with memory interface
      o include the path
      o change the testname in vsim argument



  1. Mmeory controller has 2 interfaces
    • Host interface(implemented using Wishbone protocol) => Master interface
    • Mmeory interface(implemented using mix of SRAM, SDRAM, Flash, SCSD protocols) => Slave interface
  2. test_cs0_sram
    o Connected SRAM to CS0
    o COnfigured Memory controller for SRAM on CS0
    o generated txs to CS0
    o some issues were debugged


  1. Why we need register model in TB?
  1. How to use GVIM function

Tab .signal_name(wpif.same_signal_name),
Same thing repeats in all the lines
– then it can be implemeneted using function in GVIM

How function works:
– record pattern to a symbol
q => starts recording
do one complete pattern
q => ends the recording
– map that symbol to anotehr symbol
map some_otehr_kbd_chateracter @
10 => it will do teh function repetition 10 times


  1. test_cs0_sdram/flash/scsd
  2. Otehr funcitonal testcases
  3. code remaining TB components


  1. Size of SDRAM used
  1. When we download SDRAM from Samsung or Micron websites, they also provide datasheet for SDRAM memory
    o in the datasheet, they will provide the values of refresh, precharge, activate, write, read delay values in ns/ps
    o these values are what is exacrly trfc, trp, trcd, twr, CL
    o these values need to be programmed in to TMS register of memory controller
    o Now both memory controller and Memory are working on based on smae delay values of memory
    o both of them will work in sync
    o what will happen if they don’t work in sync?
    – memory controller will activate, memory will start getting activitated
    o if they are out of sync
    o memory controller will issue write, but memory is not activiated(it is still in process)
    o if they are sync, MCTRL knows when memory will get activitated, then only it will issue write/read
    o how does MCTRL know when to issue write?
    o TMS register will give these dtails
  2. Flash testing: Exception from spec
    • Spec mentions connecting only one Flash memory, MCTRL will do multiple write/reads for completing 32 bits access
      o this is not working in RTL => THIS IS A BUG
    • Current design supports
      o connect multuple Flash memories to add up 32 bits
      o MEM_CTRL only does one write/one read
  3. tests targeting mix of memories
    o SRAM : CS0
    o SDRAM : CS1
    o FLASH : CS2
    o SCSD : CS3
    o SDRAM : CS4
    o FLASH : CS5
    o SRAM : CS6
    o SCSD : CS7

Tomorrow session:

  1. Monitor, coverage, reference model, assertions, checker, register model

SESSION#6 (12/April)


  1. worked on functional testcases
    o connected same & different memories to all CS
    o how did we check CS is accessed?
    o mc_cs_pad_o[7:0]
    o defautl value = 8’hFF
    o if value = 8’hFD => what does it mean? CS1 selected in current operation
    = 8’b1111_1101 => bit number 1 is low(asserted)
    o if value = 8’hBF => what does it mean? CS6 selected in current operation
    = 8’b1011_1111 => CS6 is selected
    o if value = 8’hBD => what does it mean? This is illegal, because at same time multiple CS’s can’t be targeted
    o CS enabled/disabled is decided based CSC[0]th bit, which has no relation to mc_cs_pad_o


  1. for loop is procedural statement
    • hence it can’t coded outside initial block
      o there is an exception: genvar

integer i;
for (i = 0; i < 8; i=i+1) begin

genvar i;
for (i = 0; i < 8; i=i+1) begin
It is illegal because it will generate 8 statements as below:

above code can’t be coded outside initial/always block

genvar i;
for (i = 0; i < 8; i=i+1) begin
always @(posedge clk[i]) begin
q[i] = d[i];
Above code will generate
always @(posedge clk[0]) begin
q[0] = d[0];
… so on till
always @(posedge clk[7]) begin
q[7] = d[7];

//BELOW CODE IS ILLEGAL => below code will not compiler because i should be declared as genvar
integer i;
for (i = 0; i < 8; i=i+1) begin
always @(posedge clk[i]) begin
q[i] = d[i];

  1. below code will compile
    integer a ;
    integer a ;
  2. SDRAM access happens in 2 stages
  1. for other memroies, indepdenent of memroy size, MEM_CTRL can generate one address at a time to access the content


  1. we will improve existing tests
  2. we will code TB components


  1. we will improve existing tests
  1. Try below code
    tx.randomize() with {reg_mem_f == MEM; addr inside {
    }; wr_rd == 1;};

as below: below code will give constraint conflict
tx.randomize() with {reg_mem_f == MEM;
addr inside {[CS0_START:CS0_END]};
addr inside {[CS1_START:CS1_END]};
addr inside {[CS2_START:CS2_END]};
so on…
}; wr_rd == 1;};

  1. SDRAM: even if user does not write/read to the SDRAM, periodic refresh will happen
    o periodic refresh, there is signalling happens to SDRAM
    • How WB protocol works?
    • WSM
      • Wait state introduced by Master
        • Master is current busy, hence it is not able to do transaction
        • how does it indicate that it is busy?
          o by deasserteing stb_i for few clock cycles
          – if deasserteing for one clock cycle => 1 Wait state
          – if deasserteing for 3 clock cycle => 3 Wait state
    • WSS
      • how slave introduces wait states?
        o by deasserteing ack_i for few clock cycles
  1. TB functional coverage will be implemented in 2 places
    • register model ( => all the register configuration sepcific coverage will be done
    • interface specific coverage file (
      o addr value, which memroy is taregted, wr/rd, sel?
    o it is a very important component of every TB
    o reference model can be coded in any langauge as long as tool supports it(compiles that langauge)
    o reference model can be coded in Verilog/SV/C/C++
    o if refrence model is coded in C langauge, how can it be conencted to monitor and checker(coded in SV)? DPI
    o HOW Can we code reference model in C langauge?
    o reference model does not have concept of time.
    o reference model does not have clock, infact it does not have itnerface. It only gets txs as inputs.
    o everything in reference model happens in 0 time
  3. Reference model algorithm (Spec we have read, putting all those concepts in a structued manner)



  1. why do we write memory ctrl signals as pad_o and pad_i?
  1. testcase for diff mem connected data is getting corrupted? how to fig it out.
  1. Register model
  1. TMS register class imppelemntation is tricky
    reason: TMS has polymorphism kind of behavior
    tms[31:0] can mean sdram specific values, scsd specific values, flash(ascd) specific values
    we need to understand, to which type of memory current transaction is targeting, accordingly decode the register fields
  2. CP_REF_PRESCALAR : coverpoint csr_reg.ref_prescalar iff (addr_t == 32’h6000_0000) {

how many coverpoints will be there in register model covergroup?
– we need to implement coverpoint for each register field
– CSR : 5 coverpoints
– POC : none
– BA_MASK : 1 coverpoint
– CSC0 : 9 coverpoints
– one coverpoint for CSC0.SEL
– one coverpoint for CSC0.PEN
– one coverpoint for CSC0.KRO so on
– CSC1 : 9 coverpoints
– CSC2 to 7 : 9 coverpoints
– TMS : bit complex due to TMS polymorphism behavior =>
o we need to figure out the memory type, based on that implement TMS coverpoints
TMS will require 16 coverpoints
8 TMS => 16*8 = 144 coverpoints
total coverpoints in register model:
= 144 (TMS) + 72 (CSC) + 1 (ba_mask) + 5 (CSR) = 220 coverpoints
– many more cross coverpoints will be tehre (may be 40)

  1. what will happen if we don’t implmenet this covergroup?
    mc_reg_cg CP_CSC0_MEM_SIZE : coverpoint csc_regA[0].ms iff (addr_t == 32’h6000_0010) {
    bins MEM_SIZE_64Mb = {2’b00};
    bins MEM_SIZE_128Mb = {2’b01};
    bins MEM_SIZE_256Mb = {2’b10};
    bins RESERVED_MS = {2’b11};
    ABove coverpoint will tell us have we exercised all possible memory size prgoramming for CSC0?
    if we didn’t do, then our verification is not complete.
    Basic verification philosophy: anything that is not checked is a bug(it might be working, but since you didn’t check it is a bug)
    if we didn’t try 128Mb memroy connected to CSC0 => then it is a bug(memory controller may not work for 128Mb connected on CS0)
  2. clsong the holes for cross coverage is difficult?
    o coverage hole : coverage gap(bins that are not hit)
  3. Functional coverage does not tell anything about whether memory controller is working properly or not
    • it only tells whether we have exericezed all possible configurations, did we target all memor types, etc…
    • if not Functional coverage, who will tell whether MEM_CTRL is working or not? Checker
  4. If we have 100% functional coverage, then we need to check what is % of code coverage?
    lets say: code coverage = 10% => number of coverpoints in covergroup is very very less
    o we haven’t implmented all possible coverpoints
  5. If we have 100% functional coverage, then we need to check what is % of code coverage?
    lets say: code coverage = 99% => things are good, because both functional and code coverage numebrs are matching
  6. If we have 90% functional coverage, then we need to check what is % of code coverage?
    lets say: code coverage = 85% => things are good, we still have to around 15% of verification completion.
  7. If we have 20% functional coverage, then we need to check what is % of code coverage?
    lets say: code coverage = 90% => too many redundant coverpoints(most probable case), we may need to review the coverage
    o is there any RTL configurations are there?
  8. code coverage
    o RTL code coverage
    o has all lines run?
    o have all code branches have run?
    o have all signals toggled inside the design?

ex: if only SDRAm is targeted, we will get only 25% branch coverage
if (mem_type == SDRAM)
addr = 32’h1000;
else if (mem_type == SRAM)
addr = 32’h2000;
else if (mem_type == FLASH)
addr = 32’h2000;
else if (mem_type == SCSD)
addr = 32’h2000;


//when register model reset is called, all registers are resetted
function void reset();



foreach(csc_regA[i]) csc_regA[i].reset();

foreach(tms_regA[i]) tms_regA[i].reset();


  1. when we write register block in design, will all registers get written?
    o onyl the targed reister will get written, how do we get that register?
    – based on address
  2. Function coverage 40percent, and code coverage 25percent. Then sir 25percent code coverage complete out of 40 percent functional coverage?
    o 25%, 40% are not in to each otehr
    o 40% functional coverage: 40% of required scenario’s have been generated in all the testcases put togheter
    o 25% code coverage: 25% of RTL code has run(is runing or is active) for all the testcases put together
    both these are not directly related, but they have dependepcy
  3. why covergroup sampling is not called in read_reg method?
    • coverage makes sense only when we write register fileds, not when we read
  4. ralgen script
    RAL Generator script
    RAL : Regsiter abstraction Layer
    Gen: Generator
  5. How to integrate regsiter model in testbench environemtn?
    o integrate : where to instinate in the testbench?
  6. Why we are creating individual file specific log files?
    • in bigger projects, log files will be 10000’s to 1 lakh plus lines
    • by using dedeciated log, it makes it easy to debug
  7. mem monitor is complex
    o same interface supports 4 different types of memories
    o user has to figure out which type of memory is targeted
    o SRAM or SDRAM or Flash or SCSD?
    o based on this, we have to follow the corresponding timing diagram mem_mon has to be completely dynamic, it has to monitor the interface signals based on type of memory being targeted. Compare this with wb_monitor?
    o it is easy : we only have to implement wb_interface protocol only
  8. mem_mon
    • how to get which mem_type is taregted?
      from csc_reg => this will come from mc_reg model
      we also need which is cs number targeted => from interface signal(mc_cs_pad_o[7:0])



  1. complete,,, assertion coding
  2. setup regerssion
  3. debug failing tests
  4. coverage report generation, analysis


  1. SRAM timing diagram observations
  1. SDRAM
  1. BAS indicates how bank_addr, row_addr and col_addr needs to be decoded from wb_addr
    bas = 0 =>
  2. Monitoring flash requires one more forever loop
    o flash is a asynchronous memory(it does not use clock for doing txs)
    o whereas other memories use clock
    o hence flash needs to be handled differently



  1. 1. sir can you please repeat sdram in mem-mon. (conversion to mem txn).
    here what is the value for BA_MSB &BA_LSB
    (mainly line no 71,72,86)
    cur_bank_openA[active_cs] = vif.mon_cb.mc_addr_pad_o[BA_MSB:BA_LSB];
    cur_row_openA[active_cs] = vif.mon_cb.mc_addr_pad_o[ROW_ADDR_SIZE-1:0]; col_addr_t = vif.mon_cb.mc_addr_pad_o[COL_ADDR_SIZE-1:0];

In memory monitor, we will use mc_doc.pdf 14/29 page concepts, to concatenate BA, RA, CA to get the memory address.

  1. in mem-mon ,scsd read cycle a/cing to timing dia after ack, data read take lace immediatly, then in code why we have went for repeat(6) @(vif.mon_cb);

3.why we havnt used clocking blocks.


  1. assertions
  1. Black box assertions
    • create a module by name
    • Declare all the ports of mc_top.v, all ports should be input direction
    • connect the mc_assertion module(the way mc_top is connected) using mpif and wpif ports
    • write all the assertions inside file
      o Wishbone interface specific assertions
      o WB handshaking protocol
      o wb_sel check
      o it must be only 4’b0001, 4’b0010, 4’b0100, 4’b1000, 4’b1100, 4’b0011, 4’b1111
      o When wb_stb_i & wb_cyc_i are asserted, all the signals should be valid(none of them should be z or x)
      o Memory interface specific assertions
  2. WB handshaking protocol
    property wb_handshake_prop;
    @(posedge clk_i) (wb_stb_i && wb_cyc_i) |-> ##[0:15] (wb_ack_o == 1);
    WB_HANDSHAKE_PROP_CHK : assert property (wb_handshake_prop);

property wb_sel_prop;
@(posedge clk_i) (wb_stb_i && wb_cyc_i) |-> (wb_sel inside {4’b0001, 4’b0010, 4’b0100, 4’b1000, 4’b1100, 4’b0011, 4’b1111});
WB_SEL_PROP_CHK : assert property (wb_sel_prop);

  1. Code coverage is always taken on DUT
  2. complete steps of coverage generation
    vlog \
    +incdir+${PRJ_HOME}/design/verilog \
    +incdir+${PRJ_HOME}/verif/top \
    +incdir+${PRJ_HOME}/verif/wb \
    +incdir+${PRJ_HOME}/verif/mem \
    +incdir+${PRJ_HOME}/verif/ref \
    +incdir+${PRJ_HOME}/MemoryModels/sram_models/MicronSRAM \
    +incdir+${PRJ_HOME}/MemoryModels/sdram_models/4MX16 \
    +incdir+${PRJ_HOME}/MemoryModels/sdram_models/2MX32 \
    +incdir+${PRJ_HOME}/MemoryModels/SyncCS \
    +incdir+${PRJ_HOME}/MemoryModels/160b3ver \
    +define+SRAM_ALL_CS \
    +define+MS_64MBIT_BW_16 \
    vopt top +cover=fcbest -o test_sram_cs0
    vsim -coverage test_sram_cs0 -sv_seed 5894584 +testname=test_sram_cs0
    coverage save -onexit test_sram_cs0.ucdb
    add log -r sim:/top/*
    run -all
  3. Debug
    csr_r in which all lines it is on LHS

Digtial design
CMOS basics
SV langauge
UVM essentials

Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

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