- You are reading this article, since you understand importance of Verilog coding in VLSI.
- Verilog has been released as part of 2 phases: Verilog-1995, Veriog-2001
- Majority cases freshers just read Verilog language constructs and assume that they are done with Verilog preparation, actually it is not so.
- Learning Verilog would require you to implement some design examples starting from basic examples like Flipflop, counters, multiplexers, FIFO, then moving on to designs like Watchdog timer, interrupt controller, Tea vending machine, pattern detector.
- You should also focus on developing testbench environment using Verilog and run the simulation using a simulator.
- Learning Verilog is essential for various reasons.
- Majority of interviews for freshers would focus on Verilog constructs and coding design examples. Not able to do even a single example can be a reason for rejection.
- Learning Verilog, lays strong foundation for learning advanced HDVL like SystemVerilog and UVM.
- Verilog is very much similar to other programming languages like C, with some constructs that make it compatible for HW design implementation. Hence learning Verilog makes you equally comfortable with other programming languages.
What to learn
Focus on below aspects
- Learning Verilog language constructs including Verilog1995, 2001 without leaving any constructs, practice these construct usage using examples on Simulator
- Work on standard design examples with TB and simulation
Examples for practice
Every example below must be verified by writing testbench code in module tb, should be checked from waveform, only then that item is completed
- Design to be coded Various aspects to be implmented and checked
- Flipflop (Synchronous & Asynch Reset), Q, Q~ behavior code to implement flipflop Gate level code synthesis diagram Truth table
- Latch behavior code to implement flipflop Gate level code synthesis diagram Truth table
- Counter-Gray code counter, modulo, ring, johnson, up counter, down counter Truth table for each counter, derive logic to generate each bit of counter using Karnaugh maps, Implement these using Gates and Flipflop
- Behavior & Gate level implmentation using above truth table
- Implement using Binary encoding and one-hot encoding
- Validate Counter behavior using Simulation run, pattern should match counter behavior
- Shift register implementation Serial in parallel out Parallel in serial out
- Half adder, full adder, multiplexer Logical & Arithmetic comparator Substractor ALU
- Dual port memory write, read design & testbench create a dual port memory, one port of write, another for read Create TB to check dual port memory with random write/reads
- encoder, decoder, various gates using multiplexer without using multiplexer
- Primitive implementation using table, endtable FIFO with Synchronous & Asynchronous reset, latch, Multiplexer, And, XOR, etc
- Pattern detector 10110 pattern detection on serial input coming to design Implement using Moore FSM & Mealy FSM, notice change in number of states
- It requires coding a FSM to detect each pattern till we reach final pattern Write TB to randomly generate series of 0′ & 1’s, check the pattern detector
- Coin counter for tea vending machine Tea cost is 150 piase, user put 25 paise, 50 paise, 100 piase, 200piase, 500 paise denominatations, vending meachine gives tea on putting righ tmaount
- Traffic light controller(TLC) 1. Simple Traffic Light controller with Red-Yellow-Green state machine(30sec, 10sec, 60sec) format
- 2. Configurable TLC, with option to configure design in various modes a. Manual control mode b. High traffic mode c. Low traffic mode d. Blinking mode e. Option to configure TLC Red/Yellow/Green time using register programming f. Option to reset
- 3. Write a Testbench to verify both TLC’s above, confirm the behavior by writing multiple testcases using case statement TB initial block
- 4. Same TB above, write testcases in a different module as tasks, call these tasks in the TB module using case statement based testname to be run
- CRC generation code Write code to generate CRC5, CRC16 using standard CRC polynomial, use same logic to verify CRC generated
- Watchdog timer implementation 1. Design to generate system reset when design has no activity for specific time 2. Register to program WDOG timeout 3. Interface to configure registers 4. Interrupt & WDOG Rst as output 5. Extn_activity input bit to restart counter when activity happens
- 1. Write Testbench to verify WDOG_Timer 2. Verify using various scenarios 3. Confirm using waveform
- Synchronous FIFO
- Asynchronous FIFO
- Memory implementation Single port memory write-read Dual port memory write read code to initilize memory using fornt door Code to initialize using hex or binary image files
- example to showcase race condition using blocking assignments How this can be avoided using non-blocking
- system task usage $readmemh, $writememh, $readmemb, $writememb to write/read a memory through hierarchy
- $display, $monitor, $strobe Code to explain difference between them
- PLI, VPI implementation Implement CRC generation code in C language, call above method in Verilog using PLI & VPI. Also note reverse is not supported.
- Memory controller RTL understanding, architecture understanding No need to fully code
- Clock generation using forever Generate clock with 50% duty cycle Clock with 60% duty cycle
- PCIe different layer implementation Implement Transaction layer, Physical layer, and data link layer
- Interrupt Controller 1. 16 Interrupt lines as input 2. Configure interrupts with various priority levels 3. Drive out interrupt number as output to processor 4. Get handshake from processor 5. Once interrupt is serviced clear interrupt