Learning SystemVerilog


  • SystemVerilog has been released as part of 2 phases: SV-2005, SV-2012
  • Majority cases freshers just read SystemVerilog language constructs on some standard websites and assume that they are done with SystemVerilog preparation, actually it is not so. Your preparation is not complete unless you are able to code examples to explain each construct usage including OOP, datatypes, literals, arrays, interprocess synchronization, constraints, randomization, functional coverage, code coverage, assertions, etc
  • Learning SystemVerilog requires you to implement small examples for all above constructs and practice those on edaplayground.com, without these practice you will find it diffucult to answer questions targeted on coding in interviews.
  • You should also focus on developing testbench environment using SystemVerilog and run the simulation using a simulator. For this you can take a protocol or medium complex design like Memory controller, MAC, DMA controller, etc and setup testbench environment for this design. It will give you exposure to 90% of SV language constructs.
  • Learning SystemVerilog is essential for various reasons.
  • o Majority of interviews for freshers would focus on SystemVerilog based testbench development.
  • o Learning SystemVerilog, lays strong foundation for learning advanced methodologies like UVM and OVM.
  • o Verilog is very much similar to other object oriented programming languages like C++. Hence learning SystemVerilog makes you equally comfortable with other programming languages.

What to learn

Focus on below aspects
  • Learning SystemVerilog language constructs including SV2005 and 2012.
  • Work on VIP development for standard protocols like AXI & AHB
  • Work on funcitonal verification of standard desings like Memory controller, MAC, DMA controller, AXI2OCP bridge kind of examples
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