1. Write a code to generate 000111000111 pattern.

initial
forever begin
repeat(3) begin
@(posedge clk);
d = 0;
end
repeat(3) begin
@(posedge clk);
d = 1;
end
end

  1. Write the sequence item fields for AHB and explain their significance.
    o UVM and AHB

class ahb_item extends uvm_sequence_item;
rand bit [31:0] addr;
rand bit [31:0] dataQ[$]; //AHB is burst protocol, hence single tx will have multiple beats(transfers)
rand bit wr_rd;
rand bit [2:0] burst; //AHB merges burst_type and burst_len in to single field
rand bit [3:0] length; //it will make calcations and other component coding easier
rand bit [2:0] prot;
rand bit [1:0] resp;

uvm_object_utils_begin(ahb_item) uvm_field_int(addr, UVM_ALL_ON)
uvm_field_int(wr_rd, UVM_ALL_ON) uvm_field_queue_int(dataQ, UVM_ALL_ON)
uvm_field_int(burst, UVM_ALL_ON) uvm_field_int(length, UVM_ALL_ON)
uvm_field_int(prot, UVM_ALL_ON) uvm_field_int(resp, UVM_ALL_ON)
`uvm_object_utils_end

function new(string name=””);
super.new(name);
endfunction

//write some constraints
constraint dataQ_c {
dataQ.size() == length;
}
endclass

  1. Questions on Polymorphism?
    o what is Polymorphism?
    o Concept where, same class is implemented as different classes by means of inheritance, at the run time, we chose which class defintion to use.
    o what is practical use cases of Polymorphism?
    o eth_pkt, good, bad, and illegal pkts.
    o We have a TB, where same generator is generating 3 different types of pkts, if we don’t use the concept of Polymorphism, we will require 3 different mailboxs to put each type of pkt. By means of Polymorphism, all the pkts can be put in to the same mailbox, the BFM when it gets pkt from the mailbox, at run time it figures out what type of pkt is coming from mailbox. This ability of BFM to figure out the type of pkt at run time, is making the whole TB devevlopemnt easier.
  2. Write a constraint in such a way that for read tx 30% time and write transaction for 70% time.

enum {
WR=1;
RD=0;
} wr_rd_t;

rand bit wr_rd;
constraint wr_rd_c {
wr_rd dist {RD:=3, WR:=7};
}

5.Explain about AHB protocol and explain how you developed monitor part of coding.
AHB protocol:
o Is a on chip protocol which supports burst transfers.
o tranfers happen in pipelined manner with data phase of current transfer aligning with address phase of next transfer.

  1. Write SV or Verilog code for up_down counter logic.
    module up_down_counter(clk, rst, count, up_down);
    parameter WIDTH=3;
    input clk, rst;
    output reg [WIDTH-1:0] count;
    input up_down;

always @(posedge clk) begin
if (rst) count = 0;
else begin
if (up_down == UP) count = count + 1;
if (up_down == DOWN) count = count – 1;
end
end
endmodule

  1. Differences between Associative array and dynamic array. Advantages of associative array over dynamic array.

Advantages?
o Associative and Dynamic array when used in TB reference model, Dynamic array will consume lot of memory to model the DUT memory behavior, since it requires allocation to continous locations, for ex: if we are accessing location 1000, we must have allocated memory for 0-999 locations also.
o wehreas Associative array require memory allocation only for the locations that are being accessed. Hence it consumes less memory.
o This feature of of consuming less memory, can have significant positive impact on simulation speed.

  1. Differences between always and initial block
    always is a synthesizable construct, which can be used for RTL design coding.
    o always executes whenever any element of sensitivity list changes.
    o always block never completes, it is active for whole simulation.
    initial block is a non-synthesizable construct, which is used for TB development.
    o initial executes only once, that is at the start of the simulation.
    o whenver last statement in the initial block completes, initial block is exited.

module top;
always beign
$display(E1);
end

initial beign
$display(E2);
end
endmodule

  1. Write a code to reverse a string.
    o can you do same in Verilog
    o byte swapping
  2. What are the projects you have done?
    o I have worked on SPI controller, AXI VIP, DMA controller functional verification

o any project in your resume, you should be able to talk for 10 minutes on that topic.
o Development of AXI VIP

  1. what is the patten detector ,ethernet packet project can you explain?
  1. what you have done in RISC-V project?
    o I have verified some features on RISC-V
    o to verify those features, developed few testcases
    o testcases developed using RISV-V insturction set
  2. How you have debugged a buggy processor?
    o processor which has some RTL bug
    o If there is a RTL bug, it would impact one of the features
    o the corresponding testcase developed targeting this feature will fail.
    o from the simulation dump, we figure out what exactly is going wrong.
    o debuggin can be on insturction basis
  3. what is DMA controller? why we don’t include the processor here?
  1. what is the difference between fork_join,fork_joinany, fork join none(given some scenarios based on that).

scenarios:
o fork join:
o used for concurrent exectuon of TB components. Since TB functionality requires all components to run till end of simulation, we use fork join
fork
bfm.run();
gen.run();
mon.run();
cov.run();
join
o fork join_any
o to implement checks for handshaking protocol.
fork
begin
wait (ack);
$display(“got ack”);
end
begin
repeat(5) @(posedge clk);
$display(“error”);
end
join_any
disable fork;
o join_none
o to implement out of order transactions, overlapping tx behavior in any protocol, we can use join_none
forever begin
mbox.get(tx);
fork
drive_tx(tx);
join_none
end

  1. the interviewer asked me that we have 3 processes,write it in fork join. then he asked there are 10 lines of code inside each process.write a code in such a manner that all the things run parallaly and sequencially?( i dont remember the exact question but he asked something like tha)

fork
P1;
P2;
P3;
join

//statements inside each process will run sequencially
fork
begin
S1;
S2;
S3;
S4;
end
begin
S1;
S2;
S3;
S4;
end
begin
S1;
S2;
S3;
S4;
end
join

//statements inside each process will run concurrently ==> below code is called as nested fork join
fork
begin
fork
S1;
S2;
S3;
S4;
join
end
begin
fork
S1;
S2;
S3;
S4;
join
end
begin
fork
S1;
S2;
S3;
S4;
join
end
join

17.Write a constraint in such a way that address should be greater than 50 and less than 70 .
constraint addr_c {
addr inside {[51:69]};
}

  1. In a RTL code there is a memory and before the memory there is an address decoder logic.
    There are 15 banks and each bank address starts from 000 to FFF and 1-15 represents the bank number.
    I am accessing 5100 address, but there is a bug in address decoder which is making all the transactions
    that are happening to 6100 is being redirected to 5100 address and vice versa. How do you resolve this bug?
    • we can develop a test which does front door write and back door read and viceversa
    write_mem(5100, data);
    $writememh(system.ba1.mem);
    o if 5100 write happened to a wrong locaiton, we will catch that issue from the back door reads.
    o backdoor read will give me data present in 5100, which won’t match with the data we wrote.
  2. write the code for updown counter.
  3. Tell me about yourself?
    o 3-4 sentenses, education and interest in career
    I am from this place, I have complete Bachelros and masters from sepciifc college. My interest in verification domain.
  4. what all projects you have completed recent and in which project you are currently working on?
    o explain about project
    o one or two line explanation about the project
    o what was your responsbilities
    o listed down features, develop testplan
    o develop TB components
    o developed testcase targeting specific features.
  5. write the code for detecting the pattern 000111000?
    property pattern_check;
    @(posedge clk) valid_i = 1 |-> !d ##1 !d ## !d ## d ## d ## d ## !d ## !d ## !d;
    endproperty
    !d => same as d == 0
    d => same as d==1

module top(input d, input clk);
reg [8:0] pattern;
always @(posedge clk) begin
pattern = {pattern[7:0], d};
if (pattern == 9’b000111000) $display(“pattern detected”);
end
endmodule

  1. Have you worked on coverage? Where is the coverage component instantiated?
    o I have worked on both functional and code coverage analaysis.
    o FUncitonal coverage is implemented using a class, it is connected to the monitor using the mailbox.
    o coverage groups are sampled when transactions comes from monitor to the coverage.
    o coverage class is instantiated in environment.
  2. How do you test the connectivity between two blocks? Write a sample code
    o blocks are being refered to modules
    o connectivity test can be done using assertions property b1_b2_connect_check_1;
    @(posedge clk) 1 |-> (b2.a==b1.p); //even if we don’t write 1 |-> both are same
    endproperty
    property b1_b2_connect_check_2;
    @(posedge clk) (b2.b==b1.q);
    endproperty
    property b1_b2_connect_check_3;
    @(posedge clk) (b2.c==b1.r);
    endproperty

if there is 2 FF delay in p->a path:
property b1_b2_connect_check_1;
reg [1:0] p_t;
@(posedge clk) (1, p_t = b1.p) |-> ##2 (b2.a==p_t);
endproperty
assert property (b1_b2_connect_check_1);

property name_of_prop;
    @(posedge clk) antecedent |-> consequent;
        if antecedent=1 => consequent is checked in every +edge of the clock.
endproperty

VLSI flow:
o connectivity checks using assertions

  1. How do you test the clock and reset signals whether working as per requirement?
  1. checker to verify that b is going high after two clock cycles of ‘a’ is high?
    property pattern_check;
    @(posedge clk) (a == 1) |-> ##2 $rose(b);
    endproperty
  2. Driver and sequencer handshaking

Session#2 6-dec-2021

  1. write a code for detecting the pattern 0101010101 and 000111000111
    property pattern_check;
    @(posedge clk) valid_i = 1 |-> !d ##1 d ## !d ## d ## !d ## d ## !d ## d;
    endproperty
    !d => same as d == 0
    d => same as d==1
  2. Write the APB signals and explain about them??
    pclk, prst, paddr, pwdata, prdata, psel, penable, pready, pwrite, perror
    psel: which slave being targeted by the master
    penable: now the transaction is valid
    pready: slave is ready to accept the transaction
    perror: wrong behavior from slave
    pwrite: write or read
  3. What are the phases in APB and explain them??
  1. If we declare a variable in top module how will u pass that variable to other components and write a code for that??
    multiple ways to do it:

1st way:

- UVM: use uvm_config_db or uvm_resource_db
module top;
integer count=10;
initial begin
    uvm_config_db#(integer)::set(uvm_root::get(), "*", "count", count);
end
endmodule

class apb_driver;
    integer number;
    function void build_phase(uvm_phase phase);
        uvm_config_db#(integer)::get(this, "", "count", number); //number will get updated with value of count(10)
    endfunction
endclass

2nd way:

class sample;
static int count;
endclass

module top;
sample::count = 10;
endmodule

  1. At addr 100 u have to store 3 words, at addr(200) u have to store 6words and at addr(300) you have to store 30words.For this which data type will be used??

typedef string wordQ_t[$];
wordQ_t wordQAA[int]; ==> final one
wordQAA[100] = {“name1”, “name2”, “name3”};
wordQAA[200] = {“name11”, “name12”, “name13”, “name14”, “name15”, “name16”};
wordQAA[300] = {“name11”, “name21”, “name31”, “name41”, “name51”, “name61” ,…..};

  1. IF simulation is stuck at a point how will you debug. What all the debugging techniques that you have done when you are doing project??
    o check log file, to figure where simulation is stuck
    o we can use objections in UVM to get more details
    o what part of the testcase is it stuck
    o Open the test, check which feature and scenario is being targeted
    o then open the dump file and cechk the waveform to figure out if it is a design issue or TB issue
    o in case of design issue, while debugging dump, we can use the data flow and schematic tracing to root cause the issue
  2. If two threads are present in a fork join how will you synchronize it??
  1. Basic assertion questions??
    //APB protocol handshaking
    property apb_handshk_prop;
    @(posedge pclk) (psel==1 && penable==1) |-> ##[0:3] pready==1;
    endproperty
  2. There is a clock for “N” ns and there is a signal named(a). How will you write a code for how much time the signal is high and how much time the signal is low??

always @(a) begin
if (a==1) begin
rise_time = $realtime;
low_time = fall_time-rise_time;
$display(“low_time=%f”,low_time);
end
if (a==0) begin
fall_time = $realtime;
high_time = rise_time-fall_time;
$display(“high_time=%f”,high_time);
//num_cycles = high_time/TP;
end
end

  1. In AXI in which component are you working on (whether master or slave)?
    o AXI VIP project
    o we implemented both Master VIP and Slave VIP
    o connected both of them using interface
    o Master VIP gave request txs and Slave VIP responded.
  2. Can a slave generate awready after awvalid is generated? (From slave perspective)
    yes
    • as per AXI protocol handhsaking signal dependency, it is possible
  3. Can a master wait for awready before asserting awvalid? (From slave perspective)
  1. Explain different types of scenarios where awvalid and awready is asserted? – (AXI protocol)
  1. Assume a case where write and read is happening for the same address location which is initiated from the master side and all the fields i.e., the burst, len, etc all are same. What is the expected behaviour from the slave.
    o it should be error behavior
  2. In an RTL code there is a memory and before the memory there is an address decoder logic. There are 10 banks, and each bank address starts from 000 to FFF and 1-10 represents the bank number. I am accessing 5100 and 6100 bank, but there is a bug in address decoder which is making all the transactions that are happening to 6100 is being redirected to 5100 bank and vice versa. How do you resolve this bug from verification perspective?
    o Front door and back door access

43. Consider a signal which gets asserted for multiple clock cycles and we don’t know for how many clock cycles this will be asserted. How do you calculate that for how long the signal gets high?

property signal_high_time;
realtime rise_time;
//@(posedge clk) (a==1, rise_time=$realtime) |-> (a[1:$], $display(“high_time=%f”, $realtime-rise_time)); @(posedge clk) (a==1, rise_time=$realtime) |-> (a[1:$]) ##1 (a == 0, $display(“high_time=%f”, $realtime-rise_time));
endproperty
assert property (signal_high_time); // $display(“high_time=%f”, $realtime-rise_time);

  1. Consider we have a fork and there are 3 threads inside the fork. When a particular condition is met in the first thread the second thread should be skipped. How do you do it?

fork
begin
fork
begin
code
end
begin
wait (condition);
end
join_any
disable fork;
end
begin
end
begin
fork
begin
code
end
begin
wait (condition);
end
join_any
disable fork;
end
join

  1. Consider there are two separate components, and each component has a separate fork join statements. The 2nd component fork join should not be executed if a particular condition is met in the first components fork join block. How do you make this synchronization happen?

class compB;
task run();
fork
wait (sample::e.triggered());
P2;
join_any
disable fork;
endtask
endclass

  1. Write a code to generate 000111000111 pattern.
    done
  2. Write a code to generate 010101. pattern and repeat for 10 times.
    forever => repeat(10)
  3. Explain UVM testbench architecture.
    top module -> root insitnated as uvm_top -> uvm_test_top -> env -> sub_env -> agents, sbd, checker -> driver, sqr, monitor, coverage
  4. Write the sequence item fields for AHB and explain their significance.
    done
  5. What is burst size and burst type in AHB/AXI.
    burst_size = number of bytes transferred per beat(transfer)
    burst_type = are we doing incremetning burst, wrapping burst and fixed burst
  6. What is the maximum burst size supported in AXI and AHB.
    AXI: 3 bit variable => 27 = 128 bytes AHB: 3 bit variable => 27 = 128 bytes
  7. What is the 1KB boundary in AHB
    Master views the slave memory in the boundaries of 1KB each.
    • single tx should never happen to two boundaries.
      o in that case, single tx should be divided in to 2 transactions, one for 1st boundary, 2nd for next boundary.
    o AXI also has same concept, but it is 2KB boundary in AXI
  8. Write a constraint in such a way that for 100 samples for 30% of the transfer address should be 0-40 and for 70% should be greater than 40.
    constraint addr_c {
    addr dist {[0:40]:/3, [40:$]:/7};
    } randcase
    30: begin
    addr = $urandom_range(0,40);
    end
    70: begin
    addr = $urandom + 40;
    end
    endcase
  9. Write a constraint for bit wr_en, such that 0 should occur for 10 times and 1 should occur for 90 times.
    constraint wr_en_c {
    wr_en dist {0=:1, 1=:9};
    } randcase
    10: begin
    wr_en = 0;
    end
    90: begin
    wr_en = 1;
    end
    endcase
  10. draw and explain Testbench architecture of your project?
    o DMA controller TB architecture

56.if you have the pattern of sequence is 01010101…. How will you detect the sequence ? Can you write some snippet of system Verilog code ?
o assertions
can also be done using always
always @(posedge clk) begin
if (valid==1) begin
@(posedge clk);
if (d != 0) $error;
else begin
@(posedge clk);
if (d!=1) $error;
else begin
….
end
end
end
end

  1. Implement the 2:1mux using AND gate
    • not possible
      AND can’t give inverse behavior, MUX requires inverse behavior, hence not possible.
    • try with NAND gate
  2. What is interface in system Verilog? What all are subcomponents in interfaces?

59.what is the difference Between modport and clocking blocks
o modport: module port directions, it provides sense of direction to the signal inside the interfaces.
o we can define modport speciifc to various components using the interface, ex: BFM, MON, Slave
o without modport, BFM can drive design outputs also, since we didn’t define any direction.
o but by using modport, it will give error.
o Clocking block
o Input and output of signals with respect to specific component
o this is required to make sure that signals are sampled and driven properly w.r.t the clock edge.

60.write some snippet of code for clocking blocks? Ex: input a,b,c and output c,d write a code for clocking block for this inputs and output
clocking sample_cb;
default input #1 output #0;
input a, b;
input #3 c;
output d, e;
endclocking

61.you have 50 steps one day you can climb 4 steps up and 3 steps down. How many days to complete 50 steps
– 47 (46 days=> 46 steps, 47th day: 4 steps => 50)

62.what are the projects you have worked on? what is your role
o whatever projects in your resume
o prepare a short notes about design overview, interface, signals, your responsbilities

63.what is your strength on building TB or In what are all aspects you are good at while verifying

64.In AXI whether master should wait for slave to be ready or vice versa
o Both are possible (valid and ready can be made 1 in any order)

65.what are different types of arrays? when to choose particular type of array
o fixed size array, dynamic array, associative array, Queue
o implementing large memory behaivor => associative array
Various arrays are used based on specific application requirements.
Modeling a simple(small) memory : Use packed & unpacked array
reg [7:0] mem[127:0];
memory is addressed as byte addressed memory.
Modeling very large memories -> Associative Array
bit [31:0] large_mem[10000000:0]; //not suggested
bit [31:0] large_mem[int]; //correct
Modeling a packet or a frame : use packed array
reg [127:0][7:0] usb_frame; //all the bytes are stored in same location.
Whole packet/frame needs to be stored in single address location. Hence we use complete packed array only.
Fixed size packets, to be accessed sequentially -> Fixed Size Array
bit [7:0] payload[99:0]; //if payload is always 100 bytes only.
Variable sized packets and accessed sequentially -> Dynamic Array
Queues used when number of elements grow and shrink and you need search and sort functionalities. Ex : Scoreboard
Content Addressable memories(CAM) -> Associative Array
Command names and values from a file -> Associative Array using the command as a string index

66.Array indices of different values (say non-contiguous ) but array values is of variable size in bytes .In this case which array should be used
– associative array of Queue of bytes

67.how to synchronize threads in fork join. What is disable fork
– synchronize can be done using wait fork
o wait fork ensures all the triggered processes needs to complete, before we go to next statement execution
o disable fork used for terminating the processes.

68.the two threads in one fork join and 1 thread in another fork join should start executing only after those tow threads complete. How do you synchronize
o semaphore smp = new(2);
fork
begin
smp.get(1);
P1;
smp.put(1);
end
begin
smp.get(1);
P2;
smp.put(1);
end
begin
end
begin
end
join

fork
begin
    smp.get(2);
    P3;
    smp.put(2);
end
join
  1. what is an assertion? Assertion to check ON clock period
    o Check for implementing if signals are behaving as per required manner.
  2. how Testbench knows we are running the right test while passing test name in UVM_TEST_NAME
    o Its gets printed: which test is running.
  3. How phases start in UVM
    when we call run_test
  4. SV code to generate pattern of sequence is 01010… by randomizing object 10 times
    class sample;
    randc bit var;
    static bit cur;
    endclass

class gen;
sample s;
task run();
s = new();
repeat(10) begin
s.randomize() with {var != sample::cur};
$display(“s=%p”,s);
end
endtask

function void post_randomize():
sample::cur = var;
endfunction
endclass

module top;
gen gen_i = new();
initial begin
gen_i.run();
end
endmodule

  1. what is sequencer. What is virtual sequencer? why do we need it?
    • sequencer is a component that interfaces with sequence on one side and Driver on the other side.
      o when driver requests for the item, sequencer gets those items from sequence and gives it to driver.
    • virtual sequencer is the one, which don’t have its own items, it uses the sequencers below it handle the sequences
  2. How sequence starts in UVM
    o can be started in two ways
    seq.start(sqr);
    uvm_config_db#(uvm_object_wrapper)::set(this, “env.agent.sqr.run_phase”, default_sequence, seq::get_type());
    o squencer will run this sequence
  3. Suppose their multiple address in that multiple address some data(suppose 4,6,8bytes) is stored. how to store it.
    o multi dimensional array
  4. Draw and Explain the testbench which you used for your project.
  5. How master agent and slave agent communicate with each other.
    o AXI : both were connected using interface

78.If simulation gets hung or running forever. How you debugged it.
o as the person, who implemented testcase, we know how much it is supposed to run for.
o run the testcase with that much timeout
UVM_TIMEOUT=value
SV:
fork
begin
#time_delay;
end
begin
$finish;
end
join_any
o when we know that, it is timing out
o what is causing test to hang
o put disaply messages(UVM: we know from objections)
o from messages, we know, what is causing it to hang.

  1. Advantages of UVM testbench over SV testbench.
    o UVM provides pre-implemenetd base classes and macros, which makes it easy to develop the TB
    o SV, everything needs to be developed from scratch.
    o UVM provides well-defined guidelines on how to do each aspect of the testbench
    o SV, every user cna do in their own way, it makes it difficult to maintain such TB
    o UVM has lot of concepts like factory, config_db, resource_db, objections, phase, tlm, which makes TB developemnt easier.

80.What is objection.
o objection is a mechanism used by UVM TB compoentns to indciate when their funcitonality is starting and when it is ending. Based on that root decides when to end the simulation.

  1. Explain the ways you used for debugging.
    o done using log files
    o done by tracking wave form schematic or data paht
    o we can also use breakpoints by using $stop
  2. What all issue you face while building your testbench.
    o if I do everythin properly, no issues will come
  3. For read and write in AXI transaction how you build the testcase.
    task run():
    case (testname)
    “test_wr_rd” : begin
    //Write
    tx = new();
    tx.randomize() with {wr_rd == 1;};
    mbox.put(tx);
    tx_t = new tx;
    //Read
    tx = new();
    tx.randomize() with {wr_rd == 0; addr == tx_t.addr; len==tx_t.len;};
    mbox.put(tx);
    end
    endcase
    endtask
  4. Code for clock generator.
    initial begin
    clk = 0;
    forever #5 clk = ~clk;
    end
  5. Checker code to check the total time period.
    always @(posedge clk) begin
    prev_edge_time = cur_edge_time;
    cur_edge_time = $realtime;
    if (cur_edge_time – prev_edge_time != TP) $error();
    end

86.Checker code to check how much time clock is ON.

87.How D-flip flop can be used as a frequency divider i.e., f/2 and f/4. Diagram?
DFF -> TFF(using XOR gate)
TFF can be used to get f/2 clock

  1. How will u detect 10100101 sequence means whenever this sequence is flag bit should be high.
    o assertions

89.For the above sequence (10100101) draw the state diagram. And explain how overlapping and non-overlapping works.
a. What is overlapping and non-overlapping sequence detector.
overlapping: from final state, jump to S_101 state(101 is overlapping)

  1. What is Moore and Mealy State machine.
    o moore requires one additional state

List down all keywords in SV and UVM:
o what is it and how it is used?

ex:
    o what is Polymorphism, how Polymorphism used in TB?
    o what is clocking-block, how clocking-block used in TB?
    o what is illegal-bin, how illegal-bin used in TB?
    o what is parameterized class, how parameterized class used in TB?
    o what is objections, how objections used in TB?
    o what is uvm_root, how uvm_root used in TB?
    o what is config_db, how config_db used in TB?

    200 questions
        o these 200 questions will double your chance of clearing an interview.

Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.

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