20/March
- Questions based blueberry semiconductor interview:
2 signals, A, B.
Count the clock pulses when both A & B are ‘1’
SV & UVM questions
Constraint disabling
Factory
How to start sequences
Synchronization between driver and sequencer
Synchronization happens using seq_item_port and seq_item_export based TLM method calls. Sequencer is mapped to a specific sequence(or a default sequence) which has list of items to be given to driver. Driver requests for the item by calling seq_item_port.get_next_item. Sequencer provides the item(if the sequence has any items pending). Driver drives this item to DUT. Once driving this is done, it calls seq_item_port.item_done. Item_done removes the item from list.
Short answer:
Sync happens using get_next_item & item_done methods of seq_item_port. Get_next_item is called by driver to get the item and driver drives the item and calls item_done to indicate tx is completed. If sequencer does not have any other items, it stops.
Difference between Queue and mailbox
Write inline constraint
Difference between in-class constraint and inline constraint
In-class constraint is a constraint defined inside the classes. They take effect in all randomizations unless it is overriden.
enum {
SHORT,
MED,
LONG
} pkt_type_t;
Class eth_pkt;
pkt_type_t pkt_type;
byte byteQ[$];
Constaint pkt_type_c { //in-class constaint
(pkt_type == SHORT) -> (byteQ.size() < 40);
(pkt_type == MED) -> (byteQ.size() >= 40 && byteQ.size() <= 60);
(pkt_type == LONG) -> (byteQ.size() > 60);
}
endclass
Inline constraint is used along with randomize call. It is used to difference various testcases among each other.
class eth_gen;
task run();
case (testname)
“test_short_pkt” : begin
pkt.randomize() with (pkt_type == SHORT); //inline constaints
end
“test_long_pkt” : begin
pkt.randomize() with (pkt_type == LONG); //inline constaints
end
endcase
endtask
endclass
- How to write coverpoint
- Difference between virtual sequencer and virtual sequence
Virtual sequence is a type of sequence which does not have item of its own. It has only other driving sequences(ex: ahb_seq, axi_seq, etc) instinatied in it. Virtual sequencer is a sequencer which does not have any item of its own. It is called inside virtual sequence to drive various driving sequences in specific order.
ANSWER: Virtual sequencer is the sequencer used to drive the sequencers instantiated inside virtual sequence.
Class top_seq extends uvm_sequence; //non parameterized -> virtual sequence
Axi_10_tx_seq axi_seq; //these sequences have items of their own
Ahb_10_tx_seq ahb_seq;
Apb_tx_seq apb_seq;
uvm_declare_p_sequencer(top_sqr)
task body();
uvm_do_on(apb_seq, p_sequencer.apb_sqr)
fork
uvm_do_on(axi_seq, p_sequencer.axi_sqr)
uvm_do_on(ahb_seq, p_sequencer.ahb_sqr)
join
endtask
Endclass
Top_seq : is the virtual sequence
Top_sqr ; is the virtual sequencer => which is getting instantiated as p_sequencer. - Difference between virtual sequence and driving sequence
Virtual sequence does not have any items of its own. It just calls other driving sequences in specific order
Driving sequence has its own items. - Difference between p_sequencer and m_sequencer?
p_sequencer refers to virtual sequencer used for driving the sequences inside virtual sequences
o above example: top_sqr is instianted p_sequencer
m_sequencer refers to master sequencer of a actual driving sequence.
o above example: apb_sqr is the m_sequencer for apb_seq - what is config_db?
Config_db is utility class in UVM, it represents the configuration database,
which is used to store the configuration values of various TB component
parameters and it is also used to retrive these values from anywhere in the TB. This adding values and
retreving values in config_db happens using a alias and methods used are set
and get.
virtual axi_intf vif;
uvm_config_db#(virtual axi_intf)::set(this, “*”, “axi_vif”, vif);
o a entry is added in to config_db by name axi_vif, the value of entry is vif
We can retrive this value(interface handle) from anywhere in the TB:
virtual axi_intf vif_driver;
uvm_config_db#(virtual axi_intf)::get(this, “”, “axi_vif”, vif_driver);
- UVM TB Hierarchy?
top_module -> uvm_root -> uvm_test_top -> top_env -> sub_env’s, scoreboard, register_model, ref_model -> (sub-env) -> agents(master/slave) -> driver, sqr, monitor, coverage - how to stop simulation in UVM?
global_stop_request(); - Block diagram of UVM?
search UVM TB architecture in google - what are the phases in UVM?
- build_phase till report_phase
- build_phase is used to create component just below the current component
- connect_phase is used to connect the components just below the current component
- end_of_elaboration is used to do post connect operations like assign the
address values, memory range
- what is TLM?
TLM refers to Transaction Level MOdeling. It is used for connecting the
various TB components. It works on port-export based connections. - WHy TLM prefered over mailbox?
- TLM provides seemless connecton where we don’t need to pass the handle of TLM port to any component, we just need to instiatiate. We need to connect port to export in agent or similar component.
TLM provides various communication models, FIFO, Push, Pull, broadcast
TLM also provides bi-directional communication model (Same TLM connection can be used send items from sqr-> driver and driver-> sqr) - Mailbox requires user to pass the mailbox handle to the compoentns which need to be connected.
Mailbox only works on model, put the txs and get the txs
It is only one directional communication model
- Queue versue mailbox?
mailbox is blocking in nature. Which is the exact requirement for
driver and generator communication. Blocking refers to when mailbox does not
have any tx in it, driver mailbox.get method will wait till txs are available
in mailbox.
Queue is non=blocking in nature, in which queue.pop_front/back methods
do not wait it the queue is empty. it will go next step in execution without
getting the item. it will results in unwanted beahvior.
Hence we need a blocking nature between generator and driver, which
can be acheived with mailbox. - How can we use Queue to get blocking nature?
wait(queu.size() > 0);
Queue can also be used to achieve blocking nature between generator and BFM.
Generator will put items in to Queue using Queue.push_back(tx);
Driver will call below:
task run();
forever begin
wait(queue.size() > 0);
tx = queue.pop_front();
//mbox.get(tx);
drive_tx(tx);
end
endtask
Major point: get, put are tasks
all Queue methods are functions(they can’t provide blocking nature)
- Different data types in SV?
class, enum, struct, event,
integer based data types: int, integer, bit, reg, logic, shortint
string
chandle
typedef (user defined data types)
void - Diffenrent types of operator?
logical, bitwise, conditional, concatenation, replication, set
memberhsip, equality, shift, reduciton, unary, arithmetic - what is the difference == and === ?
== => it is called logial equality operator, it returns either 0,1 or x
if both the sides match => 1
if both the sides doesn’t match => 0
if any of them have x or z => x
=== => it is called case equality operator, it returns either 0, or 1
comparison also happpens for x and z also
if both the sides match => 1
if both the sides doesn’t match => 0 - what is Chandle?
It is used refer to C program pointer equilvalent in SV.
when we get a pointer through DPI calls in to SV environemtn, it is
assigned in SV as Chandle data type - Difference between shallow copy and deep copy?
- Deep copy is a manually implmeneted copy method, used to copy the object contnets in to anotehr object for complete object depth.
- shallow copy is a SV provided copy method, used to copy the object contnets only yhe top level(all the object values will be copied)
- if there is a object in side the object, only yhe object handle will be copied in shallow copy, where as full object contents will be copied in deep copy
- How to check wrong address access issues in memory?
if we are writing/reading to 0000, write/read is happening to 0001?
SOlution: do front door write and back door read and compare the results or viceversa - why virtual interface?
- Interface is the data type used to connect various components like DUT,
Monitor and BFM. Physical interface represents the physical memory
allocation of this itnerface fields. virtual interface refers to the handle
pointing to above memory allocaiton. Virtual interface makes sure that
multiple memory allocation does not happen for same interface. - BFM and Monitor will be accessing the interface fields using virtual interface handle.
- Interface is static data type, as soon we insitnatiate , it creates a memory => virtual keyword is used to indicate that do not allocate the memory, rather a ahndle will be assigned
- what is the difference between blocking and non-blocking?
- blocking statements, RHS value is captured and assinged to the LHS variable of the statmenet at the same time, hence the next statmente exeuciton is blocked till current statmente complete
- non-blocking statements, RHS value is captured at current time and assinged to the LHS variable of the statmenet at the end of time step, hence the next statmente exeuciton is not blocked till current statmente complete
initial begin
a <= b;
b <= a;
$display(); //old values of a & b will be pritned
end
initial begin
a <= b;
b <= a;
#2;
$display(); //new values of a & b will be pritned
end
- non-blocking can’t be used in function
- funciton is used to infer combinational logic. Only blocking statmentes apply for combinational logic.
tasks can have mix of blocking and non-blocking
- what is the use of clocking block?
- clocking block is used inside interface. It is used by BFM and monitor for
driving and sampling of design inputs and outputs as per skew specified in
clocking block. it helps avoid possible race conditions during input driving
and sampling.
SV QUESTIONS: (For all the questions below write down short description and practical example wherever applicable)
- CLASS
what is difference between class and object?
class is a definition of data type
object is the insitnation of the class data type
ex: class eth_pkt;
bit [47:0] da;
endclass
eth_pkt pkt; //pkt is the object
what is inheritance?
what is polymorphism?
what is encapsulation?
what is parameterized class?
what is interface class?
what is abstract class?
what is static data type inside class?
what is virtual methods in class?
what is static method?
what is shallow copy?
what is deep copy?
what is $cast?
what is new?
what is constructor?
what is local, protected, public?
what is automatic?
what is extern method?
what is difference between task, function?
what is score resolution operator?
what is nested class?
what is pure virtual function?
what is static and dynamic casting?
what is super and this?
what is constaint overriding?
what is funciton/task overriding?
what is property overriding?
what is rand and randc?
what is pass by value and pass by reference?
what are different scope of variables? global/local/module
what is difference between overriding and overloading? - OPERATORS
- DATA TYPES
- IPC
- ARRAYS
- FUNCTIONAL/CODE COVERAGE
- CALLBACK
- RANDOMIZATION
- CONSTRAINTS
- ASSERTIONS
- Interface
- DPI
- Scheduling
- fork join
- MAILBOX
################################################################
22/MARCH
- SV
- Digital
- difference between latch and FF, with example
o latch is level sensitive storage element, when the enable signal is high latch captures the input value, when enable is low, it holds the value
o FF is edge sensitive storage element - verilog code for latch & FF
always @(enable or d_in) begin
if (enable == 1) begin
d_out = d_in
end
end
FF:
always @(posedge clk) begin
d_out <= d_in
end - how many address lines for 16KB memory
whether the memory is 32 bit data bus or 8 bit data bus.
If the memory is word addressed:
32 bit data bus: each 32 bit is addressed by 1 address =>
16KB = 16 * 1024 * B = 4 * 1024 * Words(32 bits) = 4096 Words
each word requires 1 address => 16KB = 12 address bits
If the memory is byte addressed:
8 bit data bus: each 8 bit is addressed by 1 address =>
16KB = 16 * 1024 * B (we should not convert to words)
each word requires 1 address => 16KB = 14 address bits - 2 Diode and 1 resistor => what is it?
o https://electronicsarea.com/or-and-and-logic-gates-with-diodes/ - Implement a circuit for 10001 detector (using DFF)
o 5 FF’s
o one-hot encoding
o FF#0
write down State machine
list down all possible transitions to a state(use and gates to implement each transition, use OR gate to OR all AND gate outputs)
OR output is input to the FF - Minimization of boolean expressions
- K map => fill the elements => then group -> minimize
- demorgan theorems
- maximum decimal value for Byte(signed / unsinged)
- -128 (lowest value), 127(highest value)
- signed data type
byte b;
b = 255;
$display(b);
if byte has to store 255,
unsigned byte b; - frequency dividor circuit(2, 4)
/2 => TFF
/4 => TFF back to back - dividor by 3:
- logics using Mux, Nand, NOR
XOR using MUX => how many : 2
NOR using MUX => how many : 1
XNOR using MUX => 2 - Ax square + Bx + c circuit implementation
o use adder and multiplier
- C program
- C program for printing prime number between 1 to 100
*/
include
int main()
{
printf(“Hello World”);
int check_prime(int a) {
int prime_f = 1;
int quis;
for (int i = 2; i <= (a+1)/2; i=i+1) {
quis = (a % i);
if (quis == 0) {
prime_f = 0;
}
}
return prime_f;
}
for (int j = 0; j < 100; j=j+1) {
if (check_prime(j) == 1) {
printf ("j=%d\n", j);
}
}
return 0;
}
- Verilog
- if else and case difference
- Mux using tertinary operator
y = (s == 1) ? a : b;
4 x 1 mux using conditional operator - difference between BA, NBA
- aptitude
- SV
- write a code for generating a random number between 1.2 to 1.4
real r;
r = $urandom_range(120,140)/100.00;
- what is soft constraint?
- these are the type of constraints that can be overriden by inline constraints or constraints written in inherited class
ex:
class sample;
rand int a;
constraint range_c {
soft a > 100; a < 200;
}
endclass
sample s_inst;
s_inst = new();
s_inst.randomize() with {a == 250;};
- intA, dynamic array, size = 5, all the elements between 10 and 20
sample s_inst;
function new();
intA = new[5];
endfunction
constraint intA_c {
foreach (intA[j]) {
intA[j] >= 10; intA[j] <= 20;
}
}
- what is solve before constraint? constraint ordering?
These are the constraints which are used to tell the tool to solve a random
variable before another random varibales, so that variable dependency in other
constraints is addressed.
EX:
constraint pkt_type_c {
(pkt_type == SMALL) -> (len < 20);
(pkt_type == LARGE) -> (len > 20);
}
constraint pkt_len_order_c {
solve pkt_type before len;
} - interface with ports, clk, rst, d_in(8), valid_i(1), ready_o, d_out(8), valid_o, ready_i
write the complete interface code
interface eth_intf(input logic clk, rst);
logic [7:0] d_in, d_out;
logic valid_i, valid_o, ready_i, ready_o;
clocking dut_cb@(posedge clk);
default input #1 output #2;
input clk, rst;
input d_in, valid_i, ready_o;
output d_out, valid_o, ready_i;
endclocking
clocking bfm_cb@(posedge clk);
default input #1 output #2;
input clk, rst;
output d_in, valid_i, ready_o;
input d_out, valid_o, ready_i;
endclocking
clocking mon_cb@(posedge clk);
default input #1 output #2;
input clk, rst;
input d_in, valid_i, ready_o;
input d_out, valid_o, ready_i;
endclocking
modport dut_mp(clocking dut_cb);
modport bfm_mp(clocking bfm_cb);
modport mon_mp(clocking mon_cb);
endinterface
- Instinate above interface is top most module
pass it as new argument to env class, env to bfm(new), assign to vritual interface inside bfm
module top;
reg clk, rst;
eth_intf pif(clk, rst);
eth_env env;
initial begin
env = new(pif);
end
endmodule
class eth_env;
eth_bfm bfm;
function new(virtual eth_intf vif_l);
bfm = new(vif_l);
endfunction
endclass
class eth_bfm;
virtual eth_intf.bfm_mp vif;
function new(virtual eth_intf vif_l);
vif = vif_l;
endfunction
endclass
- what does options.auto_bin_max does?
maximum number of bins that will be automatically created, default is 64 - write a code for declaring 2 eth_pkt arrays, one dynamic array, anotehr
Queue, fill 5 random pkts in each, compare them one pkt to anotehr from array
and Queue
eth_pkt pktDA[];
eth_pkt pktQ[$];
eth_pkt pkt;
initial begin
pktDA = new[5]; //this does not create pkt handles, it only allocates 5 spaces
foreach (pktDA[i]) begin
pktDA[i] = new(); //allocating pkt in to each space
pkt = new();
pktQ.push_back(pkt);
end
end
Homework: ethernet switch verificaiton
- does constraints work on real numbers?