[vc_row][vc_column][vc_row_inner][vc_column_inner][vc_column_text]Student support requests
Website Missing List
Mentor Tracking
Course Enquiries
Certificate Requests
Certificate Request form
Scratch
Video access
Vgo list
Placements: PD, FE, DFT, Layout (update in this sheet)
Feedback Folder
Invoice Raised to clients
Student Cheque Deposits
Institute Process folder
Institute Process document & notes
WP Admin
Institute Pending
Fee Refund
VPN Access
Course Press Physical Design Search
SOCDV
ASSIGNMENT STATUS:
VERILOG
SYSTEMVERILOG
UVM
PD BASICS
PD MAIN
DFT
ANALOG LAYOUT
FRONT END MISC(DIGITAL+UNIX+SCRIPTING)
Material Sharing:
Systemverilog
verilog Presentation
verilog Course material
PD Material-1
PD Material-2
VIDEO SHARING
Front end training(Verilog/SV/UVM) Video sharing
Questasim Usage Video
GVIM Usage Video
Back end training(Physical Design) Video sharing
ICC Invoke steps Video
ICC Usage Video
FE COURSES: Access to below 6 courses to all VLSI Front end students
Verilog: Add student
SystemVerilog: Add student
Digital Design: Add student
UNIX: Add student
UVM: Add student
PERL Training: Add student
FE COURSES: Not part of VLSI Front end course
SOC Design and Verification: Add student
ARM Architecture Training: Add student
Physical Design Course:
Physical Design Basics: Add student
Physical Design Main(Ahmed, JUNE-2018): Add student
Physical Design Main(Abhay, 11-AUG-2018): Add student
Physical Design Main(Pavan, May-2018): Add student
Physical Design Main(Nag, Aug-2018): Add student
Physical Design(Ziyual, Aug-2018): Add student
Volcano Project details steps: Add student
DFT Course:
DFT: Add student
Custom Layout Course:
Physical Design Basics: Add student
Protocol Training Course:
USB2.0 Functional verification: Add student
PCIe Protocol Training: Add student
DDR Protocol Training: Add student
USB3.0 Protocol Training: Add student
Scripting Course:
TCL Training: Add student
PERL Training: Add student[/vc_column_text][/vc_column_inner][/vc_row_inner][/vc_column][/vc_row]