1. How GLS differs from STA
  2. How GLS TB setup differs from RTL TB
  3. What are steps in porting RTL TB to GLS
  4. what is SDF, who provides sdf to GLS team
  5. Why do we use force files in GLS
  6. What are non resettable flops and their significance in GLS
  7. What is 0 – delay simulations and timing simulations, how they differ. Why 0-delay simulations are important
  8. Some companies only does gls signoff with 0-delay simulation, justify the same
  9. What are various timing simulation corners, how is it related to PVT corners
  10. What type of timing simulations catch setup violations, which catch hold violations
  11. If a test is failing in gls run, what is the debug procedure
  12. When there is a x propagation in SOC GLS runs, test invariably hangs. Explain.
  13. How do we debug timing violations in gls runs. How setup time violations are fixed? How hold time violations are fixed?
  14. Can setup violations and hold time violations be fixed by GLS verification engineer in testbench. If not how these are fixed.
  15. What is timing ECO. how does these impact GLS simulations?
  16. What is functional Eco. How they impact GLS simulations
  17. What is base tape out and metal tape out. How these are related to GLS simulations.
  18. What power aware GLS runs, how they are different from normal gls runs.
  19. What are the different reasons why x propagation happens in GLS runs.
  20. What is the tool option used for disabling timing checks.
  21. What does no notify tool option does
  22. Why gls simulations are long running compared to rtl
  23. RTL Coding style suppresss x propagation, where as GLS net list propagates x propagation, illustrate using an example.
  24. What is SDF annotation. What are the issues faced during annotation.
  25. What is zero delay loop. Significance in gls runs. How do we fix these issues.
  26. If DFF output gives unwanted behavior, with all inputs proper. How do you fix these kind of issues
  27. What are the contents of SDF
  28. What are the different types of timing checks in timing simulations
  29. How do you debug x propagation in gls simulations
  30. How do you identify gls tests from RTL test plan
  31. Write a vcs simulator force file for generating a clock at 100mhz frequency
  32. What is the difference between force release and force deposit
    Where do we use these.
  33. Write a force file to replicate a signal behavior on another port in net list.
  34. What is flattened net list and how it impacts GLS tests
  35. What is synchronizer flops. How they are related to GLS.
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