Student planning to pursue course in following domains should attempt VLSI Back end training entrance test:

VLSI Back end training entrance test

Student planning to pursue course in following domains should attempt VLSI Front end training entrance test:

VLSI Front end training entrance test

SV Entrance test for students who plan to take Systemverilog training directly(skipping Verilog training)

Systemverilog entrance test

UVM Entrance test

UVM entrance test

Course Registration