GLS, UPF, Power aware simulations

  1. what is GLS?
    o Gate level simulation
    o
  2. how it differs from RTL simulation?
    o RTL simulation: design code used is RTL code
    o GLS simulation: design code used is gate level netlist

module tb;
dma_ctrl dut(); //RTL simulation: dma_ctrl will be RTL code
dma_ctrl dut(); //GLS simulation: dma_ctrl will be Gate level code
endmodule

  1. Gate level netlist, Gate level code?
    o represenation of design in terms of gates.

module dff(clk, rst, d, q);
always @(posedge clk) begin
if (rst) q <= 0;
else q <= d
end
endmodule

When we do with Gate level code?
module dff(clk, rst, d, q);
nand g1();
..
nand g9();
endmodule
netlist = net + list => list of nets

  1. I don;t see any difference, why separate domain called as ‘GLS’?
    o technically both RTL and GLS simulaton are meant for same purpose.
    o they happen at different times in the flow
    o RTL is availble almost from 2nd week of the project
    o GLS netlist is available only after synthesis
    o one more GLS netlist available after physical design
  2. What makes GLS difficult?
    o GLS simulations are very slow
    o RTL simulation : 1 hour
    o GLS simulation : 3 – 4 hours
    o more simulation events
    o GLS simulation are difficult to debug
    o GLS netlist with 1000000 gates, debugging this logic => essentially why GLS is difficult
    o GLS everything is big in size
    o netlist is big
    o waveform dumping is big
    o runtime is big
    o GLS has different possibilities
    o 0-delay simulation
    o timing simulation
    o When we convert RTL to Gate level netlist, overall hierarchies change.
    o whatever hierarchies we know from RTL code.
    o GLS hierarchies can be different
  3. what is simulation event?
    o timestep divided in to 13 regions
    a = b + c; //one simulation event
  4. what is 0-delay simulation and timing simulation?
    o every gate has a delay
    o every wire(net) has a delay
  5. 0-delay simulation
    o it is run immedieately after synthesis is done
    o but physical design is not yet done => we don’t have delay values
    o whatever simulation we run using only netlist(without any delays) is called as 0-delay simulation or Unit delay simulations.
    o since we are not taking in to account delays, it is mostly used to check the netlist funcitonality
    o is it working similar to RTL code.
  6. timing simulations
    o run once Physical design is done.
    o placement and routing flow.
    o based on these, physical design engineer provides ‘SDF’ file
    o SDF: Standard Delay Format
    o timing simulations are run with both netlist and SDF used togehter
    o $sdf_annotate
  7. annotation
  8. benefits of timing simulations
    o it will indicate if there are any setup and hold timing violations.
  9. What is UPF? how it gets related to GLS?
    UPF : Unified Power Format
    SOC:
    o lot of voltage domains
    o each voltage domain having multiple power domain
    o each power domain working on multiple clock domain
  10. why voltage is requied?
    • if VDD is 1.8V, then that transistor belongs to 1.8V voltage domain
      for a block working at 2.5V
      logic 0 range: 0 to 1.2 V
      logic 1 range: 1.3 to 2.5 V
      logic 0 signal goes from 2.5V domain to 1.2V domain? what issues are faced?
      o logic 0 in 2.5, can be 1 Volt(~logic 0)
      o 1V when goes to 1.2V => what it gets treated as? logic 1
    • to solve above problem, we use ‘level shifter’
      • 1/2.5 * 1.2 = 0.48
      • voltage signal that goes in to 1.2V domain will be 0.48(not 1)
    • can we manage with only 1 level shifter in whole SOC?
      o 1000’s of level shifter are required
      o they are all distributed across the chip
  11. analogy
    all people are in range of 0 to 3meters
    more than 1.5 meters is treated as long person
    less than 1.5 meters is treated as short person all people are in range of 0 to 1.5 meters
    more than 0.75 meters is treated as long person
    less than 0.75 meters is treated as short person 1.2 meters height person goes to other city(2nd city)
    o original town: short(~logic 0)
    o other city: 1.2>0.75 => long person (~logic 1)
  12. SOC = gates + wires(nets) + level shifters + isolation cells + clock gating cells
  13. Each voltage domain is further divided in to multiple power domains
    turn off the MCB => no possiblity of power consumption
    o power domain that is cut off voltage
    o it can start with some unknown state (due to charge transfer)
    charge => voltage
    o block functionality becomes undefined due to unknown initial state
    o use isolation cells between one block to other block connection.
    o ensures that 1st block that is funcitonal will not affect the power down blocks
  14. each power domain or voltage domain can further be divided in to multiple clock domains
    o Asynchronous FIFO: 2 clock domains
    o There are time where we don’t want one clock to be running
    o cutting off the clock, helps is reducing power consumption.
    o cutting of clock is done using ‘clock gating logic’
  15. UPF
    o unified power format tells where are in the design do we require ‘level shifters’, ‘isolation cells’, clock gate cells’
    o how many are required
    o exact geometric position
  16. Concept of UPF is required for everyone in the VLSI design flow
    o starting from architect
    o RTL integration engineer
    o as per architect instructions, he will place all these components in to the SOC.
    o even Physical design engineer needs to physically place those cells in the chip. o to ensure that, everyone in the flow(VLSI design flow starting from spec to fabrication) should be on ‘same page’ with respect to where these cells should be present.
    o format for specifying that is called as ‘UPF’
    o UPF is lanauge(~English)
    o this language tells how to specify a ‘level shifter’, it position, voltage levels used
    o this language tells how to specify a ‘isolation cells’, it position
  17. why is it important for a verification engineer?
    o analogy:
    o Juice with some ingridents => it is good
    o some more ingridents to that preparation => these can impact the quality
    o PAGLS
    o Power aware GLS
    o GLS simulation run along with UPF file annotated.
    o annotation: UPF file will tell where are level shifter, IS, CG cells will come in to the design.
    o run the simulation with that updated behavior
    o then check if simulation are running fine. => PAGLS
  18. power aware simulations
    low power verification
    UPF simulations
    o all these terms are refering to running simulation with UPF file taken in to consideration.
  19. Questasim or VCS or NCSIM will tell, how to map UPF in to design
    o Questasim power aware simulation
    o how to import UPF file
    o how to map this file contents to the gate level netlist
    o then this becomes, UPF simulations.

SESSION#2 : UVM RAL, Register model, register verification, register backdoor access testcases

UVM RAL, RV(register verification, RDL), backdoor register access

  1. RAL
    o Register Abstraction Layer why register model is required?
    Design output = function(inputs applied, register programming inside the design)
    reference model output = function(inputs tx coming from monitor) ===> WRONG
    reference model output = function(inputs tx coming from monitor, SOMETHING ELSE) ===> correct
    SOMETHING ELSE?? what it should be?
    o Register model(which is the replica of the design registers)
    reference model output = function(inputs tx coming from monitor, Register model) ===> correct concepts used for developing register model, is called as ‘Register Abstraction Layer’
    o base classes that are used
    uvm_reg, uvm_reg_block, uvm_reg_field, uvm_mem when you get in to the project?
    o 99% of the times, register model is already integrated in to the TB.
    o register model is also developed
    o register model is also integrated in to the TB
    o what is that I have to do w.r.t register model?
    o testcase development related to your block how can we use register model for testcase development?
  2. How does register model looks like?
    o .sv file, implemented as various classes
    o all register definitions are implemented as ‘class’
    reg [31:0] priority_reg;
    class priority_reg;
    endclass

3Q. without macro if we use rm, automatically it will do the function of macro?

4Q. should write method be explicitly defined in this code?
o no
o this write method is automatically implmeneted in UVM base classes

  1. Every project compolsorily has register model.
  2. register model usage
    o how to develop register model & register adapter
    o developed using a PERL or Python script
    o IPXACT definition of design is input to the script
    o generates register model definition
    o how to integrate register model in to the TB
    o 5 minutes task => this you don’t need to know => one top level TB integration person will do this.
    dma_ctrl_reg_block reg_block; //instantiating register model inside dma_env
    dma_ctrl_reg_adapter reg_adapter; //adapter?
    reg_block = dma_ctrl_reg_block::type_id::create(“reg_block”); //creating the register model
    reg_block.build(); //building the register model infrasturctue
    uvm_resource_db#(dma_ctrl_reg_block)::set(“GLOBAL”, “REG_BLOCK”, reg_block, this); //adding register model in to the resource database, so that anyone can access it from anywhere in TB
    reg_adapter = dma_ctrl_reg_adapter::type_id::create(“reg_adapter”);
    reg_block.apb_map.set_sequencer(apb_agent_i.sqr, reg_adapter); //mapping register model to the sequencer and adapter //lets our project is : USB_CTRL
    usb_ctrl_reg_block reg_block; //instantiating register model inside dma_env
    usb_ctrl_reg_adapter reg_adapter; //adapter?
    reg_block = usb_ctrl_reg_block::type_id::create(“reg_block”); //creating the register model
    reg_block.build(); //building the register model infrasturctue
    uvm_resource_db#(usb_ctrl_reg_block)::set(“GLOBAL”, “REG_BLOCK”, reg_block, this); //adding register model in to the resource database, so that anyone can access it from anywhere in TB
    reg_adapter = usb_ctrl_reg_adapter::type_id::create(“reg_adapter”);
    reg_block.apb_map.set_sequencer(apb_agent_i.sqr, reg_adapter); //mapping register model to the sequencer and adapter o how to use register model for TB development and testcase coding
    o this is where you will be working 99% of the time.
    o atleast two ways:
    – testcase development
    `uvm_do_with(tx, {tx.addr==register_addr; tx.data==write_data; tx.wr_rd==1;})
    dma_ctrl_rm.ch0_dma_reg0.write(status, write_data);
    – scoreboard or reference model implementation
    o UVM register model has many in-built methods which makes it easy to do register value comparison
  3. RV(register verification, RDL) using UVM register model

o front door write, front door read testcase

class dma_uvm_reg_backdoor_wr_rd_seq extends apb_base_seq;
uvm_object_utils(dma_uvm_reg_backdoor_wr_rd_seq) NEW_OBJ

task body();
dma_ctrl_reg_block dma_rm; //310 registers
if(!uvm_resource_db #(dma_ctrl_reg_block)::read_by_name(“GLOBAL”, “REG_BLOCK”, dma_rm, this)) begin
uvm_error("resource_db", "not able to get register model handle"); end dma_rm.get_registers(dma_regs); //get all the register handles from dma_rm in to dma_regs Queue // Write random data and check read back (10 times) //FRONT DOOT ACCESS register write-read test sequence repeat(10) begin dma_regs.shuffle(); //shuffling so that registers are accessed in random order foreach(dma_regs[i]) begin if(!this.randomize()) begin uvm_error(“body”, “randomization error”)
end
dma_regs[i].poke(status, data, .parent(this));
end
dma_regs.shuffle(); //shuffling so that reads are done in different order compared to the order in which writes are done.
foreach(dma_regs[i]) begin
ref_data = dma_regs[i].get(); //get the desired value of the register from the register model(in Reference model in the TB)
dma_regs[i].peek(status, data, .parent(this)); //get the register value from DUT register
if(ref_data != data) begin //register write data is not matching with read data
`uvm_error(“REG_TEST_SEQ:”, $sformatf(“get/read: Read error for %s: Expected: %0h Actual: %0h”, dma_regs[i].get_name(), ref_data, data))
errors++;
end
end
end
endtask
endclass

  1. what is backdoor acces?
    o for backdoor access to work, what is very important?
    o accessing by hierarchy
    dma_ctlr.csr.poke(status, 100);
    //dut.s1.s2.csr = 100;
    //above line is what is actually happening.
    //during regsiter model development, we have done this mapping
  2. They will assign a block to you.
    o they will ask you to run register access testcases
    o run the test
    ./run_test.pl -testname dma_ctrl_reg_wr_rd_test -timeout 10ns
    o test passes
    o confirm from the waveform that test is actually passing
    o test may fail
    o it generates a log file
    o DMA_CTRL/Verif/SIM/transcript
    o DMA_CTRL/Verif/SIM/run.log
    o open the log file
    o search for Error or UVM_ERROR
    o figure out why error is coming
    o which register is mismatching.
    o what is causing it to mismatch?
    o debug that mismatch?
    o design issue?
    o specification have mentioned wrong value?
    o debug all the errors
    o fix the TB or get the RTL code fixed
    o once everything is fixed
    o run the test again
    o this process continues till ‘testcase’ passes
    o How they will measure your performance?
    o If given 20 testcases to you?
    o how quickly do run debug those testcases, report errors, get those errors fixed
    o get all 20 testcases passing.

Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.

Course Registration