1. Radix and Number system

a. Questions based on radix. size. value

                i. Fond the value of X, (135)x + (144)x = (214)x + 2

                ii. (470.56)16 – (297.55)16

                iii. (271.05)8 – (475.235)16

                iv. if(136)10 = (210)x what is x

                v. (88)16 = (?)10

                vi. (1551/443)r = (3)10

                vii. (104010401)8 = (11011011)?

                viii. 156088/123)10 = (710)r what is r

                ix. (221505)8 = (12345)r what is r

                x. (512/41)r = 10, what is r.

                xi. (1A53)16= ?

                xii. (734)8 = (?)16 .

b. If (84)x (in base-x number system) is equal to (64)y (in base-y number system), then possible values of x and y  are

(A) 12, 9

                        (B) 6, 8

(C) 9, 12

(D) 12, 18

Answer- C

c.  Consider the addition of number with different bases

                                i. (x)7 + (y)8 +(w)10 +(z)5 = (k)9

                                ii. if x = 36, y = 67, w = 98, k = 241 then find the value of z.

d.The minimum decimal equivalent of the number

(21A)x is

(A) 538

(B) 1032

(C) 263

(D) 220

Answer- C

form are P = 11101101 and Q = 11100110. If Q

is subtracted from P, the value obtained in signed 2’s

complement form is

(A) 100000111

(B) 00000111

(C) 11111001

(D) 111111001

Answer- B

represented in two’s complement format. The

sum of X and Y represented in 2’s complement format

using 6 bits is:

(A) 100111

(B) 001000

(C) 000111

                                                (D) 101001

Answer- C

is a3 a2 a1 a0. The same number, when stored using

8 bits will appear like.

(A) 0000 a3 a2 a1 a0

(B) a3’ a3’ a3’ a3’ a3 a2 a1 a0

(C) a3 a2 a1 a0 a3 a2 a1 a0

(D) a3 a3 a3 a3 a3 a2 a1 a0

Answer- D

c.     Gates using other gates

d.    Implement Buffer and inverter using XOR gates

e.    Implement 2 bit comparator using 1 bit comparator

f.     Applications of buffer

g.  AB+BC+CA

                                i. Implement only using NANO

                                ii. Implement only using NOR

                       h. Two I/P nand gate to inverter

                       I .Y=AB~CD + A~C~D+B~DC+~BCD using NAND gates

                       j. Implement the following function using fewer number of NOR gates F=M(23,4,6,7)

                      k. Assume an X-gate whose outputs is ~pq, if P and q are the inputs using the AND & OR gate.

                      l. Give two ways of converting a two input NAND gate to an inverter.

                   m. Convert XOR gate in to buffer and an inverter (using only one XOR gate).

                    n. The output of a logic gate is 1 when all its inputs are at logic 0. the gate is either

                                a. (A) a NAND or an EX-OR (B) an OR or an EX-NOR

                                b. (C) an AND or an EX-OR (D) a NOR or an EX-NOR

                     o. The output of an exclusive -OR gate is high if ___________ 

                     p. Give the transistor level circuit of a CMOS NAND gate.

                     q. Draw the I-V characteristics of CMOS inverter? And explain CMOS latchup?

r. When a logic gate is driving another logic gate,  the condition which must be satisfied for proper

operation is

(A) VOH > VIH and VOL > VIL

(B) VOH < VIH and VO L > VIL

(C) VOH > VIH and VOL < VIL

(D) VOH < VIH and VOL < VIL

Answer – C

    s. The minimum number of NAND gates required to implement A ⊕ B ⊕ C is

(A) 8 (B) 10 (C) 9 (D) 6

Ans: A

                     t. An OR gate has six inputs. How many input words are  there in its truth table?

(A) 6 (B) 36 (C) 32 (D) 64


u. The minimum number of two input NOR gates are required to implement the simplified value    of  the following equation

f(w, x, y, z) = ∑m(0, 1, 2, 3, 8,9 10,11)

(A) One (B) Two (C) Three (D) Four

Answer: A

v. The output of a logic gate is ‘1’, when all inputs are at  logic ‘0’. Then, the gate is either

(1) NAND or XOR gate

(2) NOR or XOR gate

(3) NOR or XNOR gate

(4) NAND or XNOR gate

(A) 1 and 2 (B) 2 and 3

(C) 3 and 4 (D) 4 and

Ans: C

w. A three-input majority gate is defined by the logic  function M(a, b, c) = ab + bc + ca. Which one of

the following gates is represented by the function

M (M (a,b,c)’,M (a,b,c),c) ?

(A) three-input NAND gate

(B) three-input XOR gate

(C) three-input NOR gate

(D) three-input XNOR gate

Ans. B

  1. For the following circuit, the output Y is

(a) P’ + Q’ + R’ + S’

(B) P+Q+R+S


(D) (P+Q)(R+S)

Answer- B

(a) Half adder

(b) XOR

                                                (c) Full adder

(d) Equality detector

Answer- D

S1: The dual of NAND function is NOR

S2: The dual of XOR function is XNOR

(A) S1 and S2 are true

(B) S1 is true

(C) S2 is true

(D) None of these

Answer: A

then how many number of NAND gates are

required? (inverted inputs are available)

(A) 3 (B) 4

(C) 5 (D) 6

 Answer: A

Equivalents in Column II shown in the following table.

(a) P-2, Q-4, R-1, S-3

(b) P-4, Q-2, R-1, S-3

(c) P-2, Q-4, R-3, S-1

 (d) P-4, Q-2, R-3, S-1

Answer- D

The output f will be

(a) (ABC’)’

(b) A’

 (c) ABC’

(d) A

Answer- D

implement one three-input EX-NOR gate function?

(a) 1

(b) 2

(c) 3

(d) 4

4.Mux based questions

  1. Bigger mux using smaller mux
    1. 5×1 mux using 2×1 mux
    1. 2.1 mux using 4xl mux
    1. Gates using mux
      1. 2 Input AND gate using mux
      1. 3 Input AND gate using MUX
      1. Design a FA using 4.1 Mux and single inverter
        1. 2X1 mux only
      1. Design FA using HA
      1. Design 4 bit FA using 2 bit FA
      1. Design 10×1 mux using 3 4X1 mux
      1. 8×1 mux using 4xl and 2×1 mux
      1. XOR using 2×1 mux
      1. XOR using NAND gate
      1. 2 input and gate usign 2×1 mux
      1. design full adder using
        1. 8×1 mux
        1. 4×1 mux
      1. Design 16×1 mux using
        1. 8×1 mux
        1. 4×1 mux
      1. design 4×1 mux using decoder and tristate buffer
      1. implement NAND gate using NOR gate
    1. use XOR gate to implement
      1. comparator
      1. inverter
    1. Mux using gates
      1. 3×1 Mux using 2X1 mux’S (2) with following selection requirement
        1. If AB==00, Select i0
        1. if AB==01, select i3
        1. if AB==10. select i2
    1. 2×1 max using NOR gate

f.     F(a,b,c,d) = M(1,2,3,5,6,8,10) using

                                                                a. 2×1 mux

                                                                b. 4×1 mux

        g. F(a.b.c.d)= M( using

                                                                a. 2×1 mux

                                                                b. 4×1 mux

                               h.    Design 8xl mux using 2:4 decoder gates

                                                i.      F(w1, w2, w3, w4, w5) = ~w1~w2w4~w5 + w1w2 +w1w3 + w1w4 + w3w4w5 using

                                                                a. 4×1 mux

                                                                b. 2×1 mux         

       j.     Implement 4×1 Mux using tri state buffer and a decoder

       k.     Design halfadder using 2×1 MUX

                      l.     what is the output for below circuit in terms x,y,z

   m. The number of control lines for a 8 – to – 1 multiplexer is?

    n. Desing a combinational logic circuit with four 2×1 mux which works as HA and FA. If control input is ‘1’ circuit should work as HA, else as HA. assuming that no complemented inputs are available

                    o. Write truth table for 3×1 Mux

p. What is the status of the inputs S0, S1, and S2 of the 74151 eight-line multiplexer in order for the output Y     to be a copy of input I5?

                                a. SO = 0, S1=1, S2=0

                                b. SO = 0, S1 =0, S2=1

                                c. S0=1, S1=1, S2=0

                                d. S0=1, S1=0, S2=1

                q. Consider the logic circuit given below

Input in all the line I13 in 16×1 Mux corresponds to o/p at line bar of 16 Demux, find the value of n.

                                r. The output of the following Multiplexer circuit is

(A) x’ + yz

(B) x’ y+ z

(C) (x’ + y)z

 (D) x’ y’ + yz + xy’z

Answer- B

(a) 1 and 2

(b) 1 and 3      

(c) 1 and 1

                                    (d) 2 and 2

Answer- C

(a) XY + X

(B) X+Y

(c)X’ + Y’

(D) X Y’ + X


(a) A’B’C



(d)A’ B’ C’

Answer- C

(a) X= AB’C’ + A’BC’ + A’B’C + ABC

(b) X= A’BC + AB’C + ABC’ + A’B’C’

(c) X= AB+BC+AC

(d) X= A’B’+B’C’+A’C’

Answer: A

shown in the following figure is (ground implies a

logic `0’)

(a) F = AND (P, Q)

(b) F = OR (P, Q)

(c) F = XNOR (P, Q)

(d) F = XOR (P, Q)

are the inputs to the 4:1 multiplexer R(MSB)

and S are control bits. The output Z can be represented


(a) PQ + PQ’S +Q’R’S’

(b) PQ’ + PQR’ +P’Q’S’

(c) PQ’R’ +P’QR +PQRS +Q’R’S’

(d) PQR’ +PQRS’ +PQ’R’S +Q’R’S’

Answer- A

  1. An 8-to-1 multiplexer is used to generate the  CARRY output of a full-adder. If the three control inputs are used as the two input bits to be added and the CARRY IN bit; how many number of data bits would need to be tied to logic `1’ status?

(a) 2

(b) 3


(d) 5

Answer- C

1. Active low (OR) inverting (AND gate)

2. Active high (OR) Non-inverting (OR gate)

                                               c.   A 5 × 32 Decoder can be constructed by using

S1: four 3 × 8 Decoders and one 2 × 4 Decoder

S2: five 2 × 4 Decoders

S3: eight 2 × 4 Decoders, one 3 × 8 Decoder

S4: four 3 × 8 Decoders

Consider all the decoders are having enable input.

(A) S1, is true alone

 (B) S1, S3, S4 are true

(C) S2, S3 are true

 (D) S1, S3 are true

Answer- D

d. To construct a 5 to 32 line decoder, how many number of 3 to 8 line decoders and 2 to 4 line decoders are required respectively without using any extra hardware?

(A) 3, 2

 (B) 4, 1

(C) 2, 4

                                                (D) 2, 2

Answer- B

  1. f (x2, x1, x0) = ?

(A) p (1, 2, 4, 5, 7)

(B) ∑(1, 2, 4, 5, 7)

(C) ∑(0, 3, 6)

(D) p (0, 2, 3, 6)

Ans: C

(A) A ⊕ D (B) A Ꙩ D

(C) A Ꙩ C (D) A ⊕ C

Answer: D

(A) 3 to 8 line decoder only

(B) 3 to 8 line decoder and one OR gate

(C) 3 to 8 line decoder and two OR gates

(D) None

Ans. C

6.            Boolean expression minimization

      a.K Maps

i. Simplify F(A, B, C, D) = S ( 0, 1, 4, 5, 7, 8, 9, 12, 13)

ii.Detention, the function F3 in the given circuit. where

a. F = sum if minterms(0,1,3,5)

b. F1 = (2,3,6,7)

c. F2 = (0,1,5)

d. Circuit

            i. Fl. f2 input to NAND => n1 is output

Ii. F3 is input to inverter  => n2 is output

iii.n1 and n2 are input to AND gate => F is output

  1. Minimal cost function F=M(3,4,5,7,9,13,14,15) using 4×1 Mux
    1.  Implement a minimal cost circuit for F = M(0,1,3,7) in SOP form. Is the circuit hazard free? If not how to rectify it to obtain a hazard free ckt?
    1. . The number of min terms for the function
      1. F(a, b, c, d, e) = b + cd is
        1. (A) 24
        1. (B) 20
        1. (C) 32
        1. (D) 16
        1. Answer- B
      1. The minimum SOP form of
        1. f (P, Q, R) = (P’ + R + Q’)(P’ + R’+ Q)(P’ + R + Q)
          1. (A) P’ + QR
          1. (B) P’ + Q
          1. (C) P’Q’ + R
          1.  (D) P
          1. Answer- A
    1.  The max term expression of a four variable even function is
      1. (A) π M (0, 2, 4, 6, 8, 10, 12, 14)
      1. (B) π M(1, 3, 5, 7, 9, 11, 13, 15)
      1. (C) π M (0, 3, 5, 6, 9, 10, 12, 15)
      1. (D) π M (1, 2, 4, 7, 8, 11, 13, 14)
      1. Answer- D
    1.  If the Boolean function f(a, b, c, d) = a + b + c + d has to be implemented with only 2 input NAND gates, then how many NAND gates are required?
      1. (A) 6
      1. (B) 7
      1. (C) 8

                                           Iv.         (D) 9

(a) 16

(b) 256

(c) 1024

(d) 65536

Answer-  D     

(A) f(A, B, C, D)

= Σ(2, 6, 10, 11, 12, 13, 14)

(B) f(A, B, C, D)

= Σ(3, 5, 7, 10, 11, 12, 13, 14)

(C) f(A, B, C, D)

= Σ(1, 2, 6, 8, 10, 12, 13, 14)

(D) f(A, B, C, D)

= Σ(1, 2, 4, 7, 8, 11, 13, 14)

Answer- D

(A) ABC + (ABC )’

(B) AB + BC + CA

(C) ABC’ + AB’C + A’BC

(D) ABC’ + A’BC’ + (ABC)’

Ans: C

  1. The Boolean function Y = AB + CD is to be realized

using only 2-input NAND gates. The minimum number

of gates required is:

(A) 2 (B) 3 (C) 4 (D) 5  

Ans: B

number of prime implicants is

(A) 2(n – 1) (B) n/2 (C) 2n (D) 2(n-1)

Ans. D

(A) 2 (B) 3 (C) 4 (D) 5

Ans. A

occur. For rest of the status, relay should be OFF. The

minimized Boolean expression notifying the relationship



(B) B’D’ + A’BD

(C) BD + AC

(D) AB + CD

Answer: B

(A) a’ + b’ + c

(B) (abc)’

(C) (a’ + b’)c’

(D) (a + b)’ + c’

Answer: B

(A) (a + b)(a’ + b’)

(B) (a’ + b)(a + b’)

(C) (a + b’)(a’ + b’)

                                                (D) (a + b)(a’ + b)

Answer: B

outputs A, B, C. When the binary input is 4, 5, 6 and 7,

the binary output is 2 less than the binary input. When

the binary input is 0, 1, 2 and 3, the output is 4 more

than the binary input the Boolean expression for output

A and C respectively are?

(A) x’ y, z

(B) x + y’, z’

(C) x, z

(D) x’ + y, z

implemented by the following 2 × 1 multiplexer then

the gate 1 and gate 2 are respectively?




      (D) NAND, OR

Answer: A

to be implemented with only 2 input NAND gates, then

how many NAND gates are required?

(A) 6 (B) 7

(C) 8 (D) 9

Answer- D

f(A, B, C, D) = AB + AC’ + C + AD + A B’C + ABC

(A) A + C’

                              (B) A’ + B’

(C) AC

(D) A + C


f(0, 0) = f(0, 1) = f(1, 1) = 1; f(1, 0) = 0  Assuming that the complements of x and y are not available, a minimum cost solution for realizing f using only two-input NOR gates and two-input OR gates (each having unit cost) would have a total cost of

(a) 1 unit

(b) 4 unit

(c) 3 unit

(d) 2 unit

Answer- D

7. Combinational circuits

  1. Binary encoding. one hot encoding
    1. Design an HA using minimum number of NAND gates
    1. Design a half substractor using half adder 
    1. Design 2 bit comparator using 1-bit
    1. Design 4 bit add-subtractor circuit
    1. Compare two 8-bit numbers without using comparator
    1. Consider the given circuit

In this circuit, the race around condition

(A) does not occur

(B) occurs when clk = 0

(C) occurs when clk = 0, A = 1 and X = Y = 1

(D) occurs when clk = 1, A = 1

Answer: D

(a) 4 (b) 6 (c) 8 (d) 10

Answer- B

The encoder has priority for higher order bits.

(a) 0111

 (b) 1000

(c) 1001

(d) 0110

Answer- A

  1. A four-bit adder-subtractor can be constructed from four full-adders and

(a) four two-input OR gates

(b) two four-input OR gates

(c) two four-input Exclusive-OR gates

(d) four two-input Exclusive-OR gates

Answer- D

  1.  Given that IC 7483 is four-bit parallel adder chip; how would you construct a 16-bit parallel adder circuit?

(a) By a cascaded arrangement of four 7483’s

(b) By a cascaded arrangement of 16 7483’s

(c) 16-bit adder cannot be constructed from 7483’s

(d) None of these

Answer- A

  1. The output Y in the circuit shown in the following

figure is always “1” when

(a) two or more of the inputs P, Q, R are “0”

(b) two or more of the inputs P, Q, R are “1”

(c) any odd number of the inputs P, Q, R is “0”

(d) any odd number of the inputs P, Q, R is “1”

Answer- B

How do we know given circuit is combinational or sequential.

      a.     Flopflop based questions


ii. perticular applications of these latches and flip-flop.

                                i. Circuits based on all above Filp-Flops

                iii. flipflop using MUX

                iv. Flip Flop using gates

                v. Designing of one type of flipflop using another type of flop flop.

                vi.  Design TFF with active low asynchronous reset by using 2:1 MUX only

vii. Design T-FF using 2×1 Mux                   

viii. Design JK-FF using 2×1 Mux

ix. T-FF to SR-FF conversion

x. Questions based on setup and hold time violations

a. 2 flops back to back connected

1. Setup violation will happen. how to resolve

                                Xi. Design D-latch using 2×1 Mux

                                xii. Convert JK-FF to D-FF

xiii. Give the characteristic tables of RS. JK, D and T flip-flops. 

xv. How many FFs are required to make a MOD-32 binary counter?

xvi. Initiate (Q0, Q1, Q2) = 100, find the modules

                                xvii. What function below circuit performs

xviii.    Give a block which takes 2 input integers and outputs them in ascending order on 2 output ports.   Using this block, design a 4 input and 4 output circuit with above behaviour(outputting in ascending order)

  1. Transmission gate-based D latch
    1. What Is Difference Between Latch and Flip-Flop?
    1. For one of the following conditions, clocked J-K flip—flop can be used as a divide-by-2 circuit when the input is applied at clock input.

(a) J = K = 1 and flip—flop has active HIGH inputs

(b) J = K = 0 and flip—flop has active HIGH inputs

(c) J = K = 1 and flip—flop has active LOW inputs

(d) J = K = 1 and flip—flop should be a negative edge-triggered one

Answer- A

(a) Q1= 0, Q2= 0

(b) Q1= 0, Q2= 1

(c) Q1= 1, Q2= 0

(d) Q1= 1, Q2= 1

  1. Answer – C
  2. The digital circuits shown in the figure works as a

(a) JK Flipflop

(b)Clocked RS Flipflop

(c)T Flipflop

(d) Ring Counter

Answer- C

(a) 010



(d) 101

Answer: B

(a) 010000




Ans- D

(a) SR flipflop with inputs X= R, Y= S

(b) SR flipflop with inputs X= S, Y= R

(c) JK flipflop with inputs X= J, Y= K

(d) JK flipflop with inputs X= K, Y= J

Answer : D

                Counter design and counter applications

                a Ring counter

                b Up counter. Down counter. up-down counter

                c. Gray code counter

                d. Johnson counter

                e Modulo counter

                f BCD counter

                g. Gray+1 up/down counter deign

                h. Up counter using Mux and FFs

                I. Behavioral code and Gate level implementation for all above counters

                j. how many FFS are required to implement mod-12 ring counter and Johnson counter

                k. Design a mod-10 binary up counter using negative edge JK FF with active low clear

l. Redesign the mod-6 gray code counter using D-FF and compare the result with JK design

m. Design a 4 bit binary to gray code converter using 2:4 decoder

n. The minimum number of FF’s required to implement a divide by 100 device? 

o. What will be the count of 5 bit binary down counter, whose initial state is 31 after 100 cycles

p .Design a 3-bit synchronous reset counter using JK-FF

q. Clock divide by 3 circuit with 50% duty cycle

r. Clock divide by 5 circuit with 50% duty cycle

s. On the fifth clock pulse, a 4-bit Johnson sequence is Q0 = 0, Q1 = 1, Q2 = 1, and Q3 = 1. On the sixth    clock pulse, the sequence is ___________ 

t. On the 3rd clock pulse, a bit johnson counter sequence is Q0=1, Q1=1, Q2=1, Q3=0, on the 4th clock pulse, the sequence is ______

u. Three, modulo-4 counters are cascaded together then  the resultant counter modulus is

(A) 3 × 4

(B) 34

(C) 4 × 4 × 4

                                    (D) 3 + 4

Answer- C

v. A binary ripple counter is to be constructed using J-K flip—flops with each flip having a propagation delay of 12 ns. The largest modulus counter that can be constructed using these flip— flops and still operate up to a clock frequency of 10 MHz is

(a) MOD-16

(b) MOD-64

(c) MOD-256

(d) MOD-8

Answer- C

(a) one AND gate

(b) one OR gate

(c) one AND gate and one OR gate

(d) two AND gates

Answer: D

(a) R = 10 ns, S = 40 ns

(b) R = 40 ns, S = 10 ns

(c) R = 10 ns, S = 30 ns

(d) R = 30 ns, S = 40 ns

Answer: B

(a) Changed from `0’ to `1’

(b) Changed from `1’ to `0’

(c) Changed in either direction

(d) Not changed

Answer – A

(A) 12

(B) 81

(C) 64

(D) 7

Answer C

  1. A counter formed with T, JK flip flops, as shown above, preset (Pr), clear (clr) are active low, asynchronous inputs, T,J,K are synchronous inputs The modulus of the counter is

(A) 4

(B) 5

(C) 6

                                    (D) 7


  1. Frequency division and multiplication
    1. Determine the frequency of output signal

                                i. 10.24Khz

                                ii. 5 Khz

                                iii. 30.24Khz

iv. 15KHz

11.          Clock frequency multiply and divide circuits

1. Freq(CIkB) = freq(ClkA)/100

a. Period(en_A) = period(Clk_A)*100, duty cycle = 50%

b. Find depth & overflow limitations

  1. Edge detectors
  2. Raising edge detector using

                a. Only combinational

                b. Only Sequential

  1. Shift registers
  2. A shift counter comprising of a cascaded arrangement of five flip—flops with inverse feedback from output of MSB flip—flop to input of LSB flip—flop is a

(a) Divide-by-32 counter

(b) Divide-by-10 counter

(c) Divide-by-5 counter

(d) Five-bit shift register

Answer – B

states Q3 Q2 Q1 Q0 = 0100 What is state Q3 Q2 Q1 Q0

after 5 clock pulses?

(A) 0111 (B) 1100

(C) 1111 (D) 1001

Answer: D

14.  State Machine based questions

1. Design an FSM for following requirements

                                i. If number of 0s > number of 1s in 3 bit sequence of input Pattern. outPut should be I

                                ii. Output always reamers “0” if sequence of two l’s are detected

2. Draw divide by 6 FSM

3. Design a FSM for clock divide by 5 with 50% duty cycle

4. circuit optimizatio

i. Number of flop required to implement a TLC with Red = 30 to 70, YEL = 20 to 50. GRN = 100 to 150. 5              possible states

                                ii. Number or FF and gates required to implement 10110 detector

5. Moore non overlapping 1001 FSM, draw FSM

(a) 32

(b) 16


(d) 4

Answer- D

7. An FSM with 6 states requires at least:

(a) 2-bit states

(b) 3-bit states

(c) 4-bit states

(d)6-bit states

Answer- B

(a) 4


(c) 8

(d) 10

Answer- (A)

15. code conversions:-

a. Write truth table for 4 bit binary to gray code converter

b.The Gray code for decimal number 6 is equivalent to _______?

c.Give the Binary, Hexadecimal. BCD, and Excess-3 code for decimal 1

d. Realize a BCD to Excess-3 code converter using a 4×10 decoder with active low (?), and minimum number of gates

c. The binary number 110011 is to be converted to Gray code. The number of gates and type required are

(A) 6, AND (B) 6, XNOR

(C) 6, XOR (D) 5, XOR

Ans. D

e. A circuit received a 4 bit excess 3 code. The function

to detect the decimal numbers 0, 1, 4, 6, 7, 8 is (assume

inputs as A, B, C, D)

A) ABC + A’C + BCD + AD

(B) CD + AD + AC + ACD

(C) CD + AD + A’C ‘+ ACD’

(D) CD + AD + AC + A’C’D’      

Ans. D

(a) BCD to binary code

(b) Binary to excess —3 code

(c) Excess —3 to Gray code

(d) Gray to Binary code

Answer- D

16. Misc.

1. Why most interrupts are active low .


3. A 2- bit  comparator gives an active high output:y, if two 2 bit words A and B are the same

4. 512X8 using 256X4

5. Draw a circuit that controls a given digital system that has 3 inputs(X1, X2, X3). It has to recognize 3 different conditions

                a. Condition A is true if X3 is true, and either X1 is true or X2 is false

                b. Condition B is true if X2 is true, and either X3 is true or X1 is false

                c. Condition C is true if X1 is true, and either X2 is true or X3 is false

                d. The circuit must produce output ‘1’ if at least 2 of above 3 condition are true. 

6. Define Clock skew, negative clock skew and positive clock skew

7. Write a Verilog swapping function without using temp variable  

8. Compare and contrast FPGA and ASIC digital designing.

9. 10 kHz clock signal having a duty cycle of 25% is used to clock a three-bit binary ripple counter.

What will be the frequency and duty cycle of true output of the MSB flip—flop?

(a) 1.25 kHz, 25%

 (c) 3.33 kHz, 25%

(d) 3.33 kHz, 50%

                        (d) 1.25 kHz, 50%

Answer- D

10. Assume the propagation delay time of 2 input gates as EXOR-20ns, AND – 10ns, OR-10ns, the propagation

delay time for sum and carry output of a full adder circuit are respectively, when all the data inputs are applied simultaneously?

(A) 30ns, 20ns

(B) 40ns, 30ns

(C) 40ns, 20ns

 (D) 20ns, 20ns

Answer- B

(A) an 8 bit converter

 (B) a 10 bit converter

(C) a 12 bit converter

 (D) a 16 bit converter

Answer- A

  1.  A D/A converter has 5 V full scale output voltage and

an accuracy of + 0.2%, the maximum error for any output

voltage will be

(A) 5 mV

(B) 10 mV

(C) 20 mV

(D) 30 mV

Answer- B

(a) I = 1, J = B (b) I = A, J = B

(c) I = B, J = 1 (d) I = B, J = 0

Answer- A

(a)10 KHz

(b) 2.5 KHz

(c) 20 KHz

(d) 5 KHz

Answer: D

(a) at 1

(b) at 0

(c) at its initial value

(d) unstable

Answer: D

(A) 5

(B) 6

(C) 4

(D) 8

Answer- D


(b) 9


(d) 16

Answer- B

(missing question)Answer- D













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