Protocol overview

• Overview
• Features
• Functional Description
• Pad Definition and Description
• Pin per byte
• LPDDR5/LPDDR5X Bank Architecture
• LPDDR5 Address Translation Table
• Bank architecture transition
• Burst Operation
• LPDDR5 SDRAM Addressing
• Speed Grade
• Burst Sequence
• WCK Clocking
• Initialization and Training
• Power-up, Initialization and Power-off Procedure
• Voltage Ramp and Device Initialization
• Dual VDD2 Rail setting (MR13 OP[7]) and its change
• Reset Initialization with Stable Power
• Power-off Sequence
• Uncontrolled Power-off Sequence
• Training
• ZQ Calibration
• ZQ Reset
• Multi-die Package Considerations
• ZQ External Resistor, Tolerance, and Capacitive Loading
• Flow Chart Examples
• Command Bus Training
• Three physical Mode Register
• Command Bus Training Mode1
• Command Bus Training Mode1 (FSP with DVFSQ enable)
• Command Bus Training Mode2
• Command Bus Training Mode2 (FSP with DVFSQ enable)
• CA VREF Training
• DQ VREF Training
• WCK2CK Leveling
• write-leveling called in LPDDR4
• Duty Cycle Adjuster (DCA)
• Duty Cycle Adjuster Range
• Relationship between WCK waveform and DCA Code Change
• The relationship between DCA Code Change and DQ output/RDQS timing
• Read DCA (Duty Cycle Adjuster)
• Duty Cycle Monitor (DCM)
• READ DQ Calibration
• WCK-DQ Training
• RDQS toggle mode
• Enhanced RDQS training mode
• Read/Write-based WCK-RDQS_t Training
• Rx Offset Calibration Training
• Simplified LPDDR5 State Diagram
• Mode Register Definition
• Mode Register Assignment and Definition in LPDDR5
• Mode Register Assignment and Definition in LPDDR5X
• Mode Register Definition
• LPDDR5 Operations
• Truth Table
• Command Truth Table
• WCK Operation
• WCK2CK Synchronization operation
• Row operation
• Read/Write Operation
• Refresh operation
• Other Operation
• Reliability & Power-optimization
• Dynamic Voltage and Frequency Scaling (DVFS)
• Data Copy Low Power Function
• Write X operation
• Post Package Repair (PPR)
• Refresh Management Command
• Refresh Management Enhancement (ARFM)
• Decision Feedback Equalization (DFE)
• Link ECC
• Single-ended mode for Clock, Write Clock and RDQS
• Enhanced WCK Always On Mode
• Pre-Emphasis for DQ output
• Rank to Rank AC Parameter
• Command Constraint and AC timing
• Effective Burst Length (BL/n) Definition
• Command Timing constraints
• Read to Write Timing (tRTW)
• Auto Precharge Command Timing Constraints
• CAS Command Timing Constraints
• Training related timing constraints
• MRR/MRW Timing Constraints
• Rank to Rank Command Timing Constraints
• AC Timing
• Core AC Timing Parameters by Speed Grade
• Core AC Timing Parameters for LPDDR5
• Core AC Timing Parameters for LPDDR5X
• Die configuration, Package ballout & Pin Definition

Course Overview

DDR5 Training Schedule

• Training is available in eLearning mode with self paced learning.
• Duration: 20+ hours
• eLearning : INR 4,000 +GST at 18%
• Live Training : INR 5,000 +GST at 18%
• Certificate of course completion