1. What is SDRAM? How does it differ from SSRAM?
  2. What is DDR SDRAM? How does it differ from SDR SDRAM?
  3. Explain SDRAM cell architecture?
    1. What is BL, WL?
  4. How does writing happen to an SDRAM cell?
  5. How does read happen from an SDRAM cell?
  6. What is double pumping in DDR?
  7. Why is SDRAM slower in access than SSRAM?
  8. When DDR is slower in access than SSRAM, why do we use DDR?
  9. How do we decide which generation of DDR is required for current application?
  10. How do we differentiate between DDR1, DDR2, DDR3 and DDR4 based on notches and their positions?
  11. What is the significance of A[10] bit?
  12. Why are Sense amplifiers used in SDR?
  13. SDR access is slow due to capacitor sensing, what is done to make it faster?
  14. What is volatile memory and nonvolatile memory? What are the examples?
  15. What does DDR200 indicate? What does PC-133 indicate?
  16. Why is DDR organized as Banks?
  17. Why is DDR organized into multiple chips to make a Rank? 
  18. Why is DDR access done in two phases?
  19. What is a row activation?
  20. What is precharge?
  21. What is ‘burst terminate’?
  22. What does the LMR indicate? What is the need for mode registers in DDR?
  23. List down how many mode registers are there in each DDR generation?
  24. What are the extended mode registers?
  25. List down various commands in DDR access, write down the CAS, RAS, WE mapping.
  26. What are the components in DDR memory architecture?
  27. What does x4, x8 and x16 indicate in DDR terminology?
  28. What is pitch?
  29. What are various voltage technologies used?
    1. Difference between LVTTL and SSTL?
  30. What is the need for column, row and bank address decoders in DDR architecture?
  31. Why does DDR require periodic refresh?
  32. What is the difference between self refresh and auto refresh?
  33. DDR is a synchronous memory and Flash is an asynchronous memory, what does it mean?
  34. What are the primary objectives when technology changes from one DDR generation to next?
  35. What is done to make sure effective BW doubles when we move from one DDR generation to next?
  36. How is the power consumption reduced from one generation of DDR to the next?
  37. What kind of signal integrity issues are seen in different DDR generations? How DDR technology addresses those?
  38. What is prefetch architecture?
  39. What are the various components in DDR subsystem architecture? What is the frequency at which these components function?
  40. Why does the DDR core frequency not change much across DDR generation?
  41. What is SIMM and DIMM?
  42. What are the different DDR packaging styles?
    1. What is the difference between TSOPII and FBGA?
  43. What are the different voltage pins used in DDR? Their significance?
  44. What is the significance of DQS and DM? How do they differ?
  45. How DDR addresses the skew arising on Data and control signals?
  46. Why is clock driven as CK and CK#?
  47. What are the CL, Trcd, Trp timing parameters in DDR
  48. What are the different techniques adopted in DDR to improve the effective throughput?
  49. What is the need for burst transfer in DDR?
  50. What are the various burst lengths supported in different DDR generations?
  51. What is auto precharge?
  52. Draw the timing diagrams for DDR write, read access.
  53. What is the need for on die termination in DDR?
  54. What is the difference between interleaved and sequential access?
  55. List down various pins at DDR core interface? 
  56. What is the difference between Channel and Rank?
  57. What is write leveling?
  58. What is Burstchop4 in DDR3?
  59. What is read leveling?
  60. What is read calibration?
  61. Why are DLLs used in DDR?
  62. What is Posted CAS, AL, WL, RL and CWL?
  63. What is the need for an ECC memory chip in DDR?
  64. What is DDR initialization? What are the various steps in initialization? Draw the DDR initialization timing diagram?
  65. What is SSTL with active termination and passive termination? Which is preferred?
  66. How clocks are provided to DDR?
  67. What is fly by topology in DDR? How does it differ from T connection?
  68. What is the maximum frequency supported by different DDR generations?
  69. What is the maximum throughput we can get from DDR3 with a 64 bit data bus?
  70. What is partial refresh in DDR3? How does it differ from auto refresh?
  71. What is self refresh? What is refresh counter required in DDR core?
  72. What are the techniques adopted in DDR for power saving?
  73. What is dynamic ODT?
  74. What is DFI?
  75. How DLL helps with proper sampling of DQ?
  76. What is a Bank group in DDR4?
  77. What is ZQ calibration?
  78. How LPDDR differs from DDR?
  79. What are multi purpose registers?
  80. What are the challenges faced as voltage is reduced in DDR generations? How are they addressed?
  81. Why are the number of banks increased from DDR2 to DDR3 and to DDR4?
  82. Why does DDR4 not use 16n-prefetch? How does its BW double w.r.t DDR3?
  83. What is the significance of Reset pin in DDR4?
  84. How Clk-DQS deskew is achieved in DDR4?
  85. How can we achieve RMW feature in DDR?
  86. Draw timing diagram for back to back write transactions.
  87. Draw timing diagram for back to back read transactions.
  88. What is OCD calibration?
  89. What are R1, R2, R3 resistors in DDR?
  90. What is partial array self refresh?
  91. What is DCC enable?
  92. What is the need for high temperature self-refresh rate enable
  93. Do we use PLL in DDR PHY? Why do we need one?
  94. DDR4 allows for DIMMs of up to 64GB, explain how does it support?
  95. What is RAS(reliability, availability and serviceability)? What is the significance?
  96. How DDR4 supports command and address parity error detection?
  97. What is read preamble training?
  98. What is write postamble?
  99. Explain different routing styles in DDR?
  100. What is post package repair in LPDDR4?
  101. What is target row refresh?
  102. What are the requirements for a DDR controller?
Course Registration