- What is SDRAM? How does it differ from SSRAM?
- What is DDR SDRAM? How does it differ from SDR SDRAM?
- Explain SDRAM cell architecture?
- What is BL, WL?
- How does writing happen to an SDRAM cell?
- How does read happen from an SDRAM cell?
- What is double pumping in DDR?
- Why is SDRAM slower in access than SSRAM?
- When DDR is slower in access than SSRAM, why do we use DDR?
- How do we decide which generation of DDR is required for current application?
- How do we differentiate between DDR1, DDR2, DDR3 and DDR4 based on notches and their positions?
- What is the significance of A[10] bit?
- Why are Sense amplifiers used in SDR?
- SDR access is slow due to capacitor sensing, what is done to make it faster?
- What is volatile memory and nonvolatile memory? What are the examples?
- What does DDR200 indicate? What does PC-133 indicate?
- Why is DDR organized as Banks?
- Why is DDR organized into multiple chips to make a Rank?
- Why is DDR access done in two phases?
- What is a row activation?
- What is precharge?
- What is ‘burst terminate’?
- What does the LMR indicate? What is the need for mode registers in DDR?
- List down how many mode registers are there in each DDR generation?
- What are the extended mode registers?
- List down various commands in DDR access, write down the CAS, RAS, WE mapping.
- What are the components in DDR memory architecture?
- What does x4, x8 and x16 indicate in DDR terminology?
- What is pitch?
- What are various voltage technologies used?
- Difference between LVTTL and SSTL?
- What is the need for column, row and bank address decoders in DDR architecture?
- Why does DDR require periodic refresh?
- What is the difference between self refresh and auto refresh?
- DDR is a synchronous memory and Flash is an asynchronous memory, what does it mean?
- What are the primary objectives when technology changes from one DDR generation to next?
- What is done to make sure effective BW doubles when we move from one DDR generation to next?
- How is the power consumption reduced from one generation of DDR to the next?
- What kind of signal integrity issues are seen in different DDR generations? How DDR technology addresses those?
- What is prefetch architecture?
- What are the various components in DDR subsystem architecture? What is the frequency at which these components function?
- Why does the DDR core frequency not change much across DDR generation?
- What is SIMM and DIMM?
- What are the different DDR packaging styles?
- What is the difference between TSOPII and FBGA?
- What are the different voltage pins used in DDR? Their significance?
- What is the significance of DQS and DM? How do they differ?
- How DDR addresses the skew arising on Data and control signals?
- Why is clock driven as CK and CK#?
- What are the CL, Trcd, Trp timing parameters in DDR
- What are the different techniques adopted in DDR to improve the effective throughput?
- What is the need for burst transfer in DDR?
- What are the various burst lengths supported in different DDR generations?
- What is auto precharge?
- Draw the timing diagrams for DDR write, read access.
- What is the need for on die termination in DDR?
- What is the difference between interleaved and sequential access?
- List down various pins at DDR core interface?
- What is the difference between Channel and Rank?
- What is write leveling?
- What is Burstchop4 in DDR3?
- What is read leveling?
- What is read calibration?
- Why are DLLs used in DDR?
- What is Posted CAS, AL, WL, RL and CWL?
- What is the need for an ECC memory chip in DDR?
- What is DDR initialization? What are the various steps in initialization? Draw the DDR initialization timing diagram?
- What is SSTL with active termination and passive termination? Which is preferred?
- How clocks are provided to DDR?
- What is fly by topology in DDR? How does it differ from T connection?
- What is the maximum frequency supported by different DDR generations?
- What is the maximum throughput we can get from DDR3 with a 64 bit data bus?
- What is partial refresh in DDR3? How does it differ from auto refresh?
- What is self refresh? What is refresh counter required in DDR core?
- What are the techniques adopted in DDR for power saving?
- What is dynamic ODT?
- What is DFI?
- How DLL helps with proper sampling of DQ?
- What is a Bank group in DDR4?
- What is ZQ calibration?
- How LPDDR differs from DDR?
- What are multi purpose registers?
- What are the challenges faced as voltage is reduced in DDR generations? How are they addressed?
- Why are the number of banks increased from DDR2 to DDR3 and to DDR4?
- Why does DDR4 not use 16n-prefetch? How does its BW double w.r.t DDR3?
- What is the significance of Reset pin in DDR4?
- How Clk-DQS deskew is achieved in DDR4?
- How can we achieve RMW feature in DDR?
- Draw timing diagram for back to back write transactions.
- Draw timing diagram for back to back read transactions.
- What is OCD calibration?
- What are R1, R2, R3 resistors in DDR?
- What is partial array self refresh?
- What is DCC enable?
- What is the need for high temperature self-refresh rate enable
- Do we use PLL in DDR PHY? Why do we need one?
- DDR4 allows for DIMMs of up to 64GB, explain how does it support?
- What is RAS(reliability, availability and serviceability)? What is the significance?
- How DDR4 supports command and address parity error detection?
- What is read preamble training?
- What is write postamble?
- Explain different routing styles in DDR?
- What is post package repair in LPDDR4?
- What is target row refresh?
- What are the requirements for a DDR controller?