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VLSI Front End Training for Freshers

VLSI Front end training for freshers making BTech & MTech freshers industry ready. Course covers following aspects.

1. VLSI & SOC Design Flow

2. UNIX & Revision Management

3. Verilog Training

4. Systemverilog fro Functional Verification

5. UVM Essentials

6. Advanced Digital Design

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Physical Design Basics

This course covers essential basics of Physical Design. This course ensures that all students in a Physical Design training batch are at same understanding level.

  • Introduction to CMOS circuits
  • MOS transistor theory, processing technology
  • Combinational circuits & Logic Design
  • Logical Effort & Power
  • Testing & Verification
  • Wires and Scaling
  • Macros

 

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Physical Design Training

 Physical Design Training

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UVM for Functional Verification

 UVM & OVM for Functional Verification (VT-VM) course is structured to enable engineers develop their skills in full breadth of UVM & OVM features in complex testbench development. VT-VM course is targeted for verification engineers who are used to SV based functional verification and would like to explore UVM & OVM based verification. Course has been framed in a way to make UVM & OVM learning a fun and interesting activity. Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple industry standard projects, all of these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VM. 

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Verilog for Design and Functional verification

 Online Training in SystemVerilog for Functional Verification is structured to enable engineers to develop their skills in full breadth of systemverilog features. VT-SVO course covers all aspects of functional verification including constrained random verification, assertion based verification and coverage driven verification. VT-SVO course has been framed to fit to every functional verification engineer requirements and also targeted for graduates aspiring to make career in VLSI Front End domain. Course approaches by teaching basic concepts to most advanced aspects of SV with relevant examples to enable easier understanding of concepts. 

 

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System Verilog for functional verification

 SystemVerilog for Functional Verification course is structured to enable engineers to develop their skills in full breadth of systemverilog features. VT-SV course covers all aspects of functional verification including constrained random verification, assertion based verification and coverage driven verification. VT-SV course has been framed to fit to every functional verification engineer requirements and also targeted for graduates aspiring to make career in VLSI Front End domain. Course approaches by teaching basic concepts to most advanced aspects of SV with relevant examples to enable easier understanding of concepts. 


VT-SV course does not just focus on teaching SV constructs and their usage. Course also puts lot of emphasis on teaching industry standard AXI protocol and developing Verification IP for same. Course also includes 1 industry standard project. All these projects are executed from scratch with students working on complete flow starting from specification reading, feature listing down, testbench architecture creation, component coding and testcase development till verification closure using coverage and regression as verification closure criteria. 

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AMBA Protocol Training

The Advanced Micro controller Bus Architecture (AMBA) bus protocols is a set of interconnect specifications from ARM that standardizes on-chip communication mechanisms between various functional blocks (or IP) for building high performance SOC designs. These designs typically have one or more micro controllers or microprocessors along with several other components—internal memory or external memory bridge, DSP, DMA, accelerators and various other peripherals like USB, UART, PCIE, I2C etc all integrated on a single chip. The primary motivation of AMBA protocols is to have a standard and efficient way to interconnecting these blocks with re-use across multiple designs.

The objectives of the AMBA protocol are to: 

• facilitate right-first-time development of embedded microcontroller products with one or more CPUs, GPUs or signal processors,

• be technology independent, to allow reuse of IP cores, peripheral and system macrocells across diverse IC processes, encourage modular system design to improve processor independence, and the development of reusable peripheral and system IP libraries

• minimize silicon infrastructure while supporting high performance and low power on-chip communication.

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Set Top Box SoC

 A set-top box (STB) or set-top unit (STU) is an information appliance device that generally contains a TV-tuner input and displays output connects to a television set and an external source of signal, turning the source signal into content in a form that can then be displayed on the television screen or other display device. They are used in cable television, satellite television, and over-the-air television systems, as well as other uses.

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USB 2.0 Protocol Training & USB Core Verification using SV, UVM

USB 2.0 has become a kind of mainstream interface technology and USB 2.0 IP core system has wide application foreground in all kinds of instrumentations and devices. Universal Serial Bus 2.0 system consists of host control chip and equipment interface control chip, i.e. peripheral devices chip. The traditional USB developing is only to develop USB peripheral devices. Peripheral device chips consist of USB2.0 transceiver macrocell interface (UTMI) circuits and interface protocol control circuits. On developing USB2.0 equipment interface control chip IP core, some hardware codes of designed peripheral devices chip need be validated, which can be completed by self-designed UTMI codes. But this simulation validating process will become very complex because self-designed UTMI codes are not always correct. In addition, this kind of simulation validation system also needs a host.

This course presents a set of detailed methods to design a validation system for simulating all kind of signal of USB2.0 interface protocol circuits, proposed methods were involved with configuring circumstance, designing test modules, processing signal transmission, developing additional tasks, introducing presented actual verification method for some main signal packages and correlative verification output results, and etc. Simulation verification results show these methods are valid, so can offer the reference for the development of USB2.0 system in all kinds of electronics instrumentations.

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Embedded Systems Training

 Embedded Systems Training

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