DDR Technology Training (DDR4)
DDR Technology Training on DDR2/3/4, LPDDR2/3/4 covers all the aspects starting from DDR ports, timing diagram, DDR statemachine, mode registers, etc.
DDR Memory Architecture
DDR, DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3, LPDDR4 Training
DDR Mode registers
Clock frequency & limitations
Command & Timing Diagrams
DDR Training: write leveling, Read leveling, CA Training, ZQ calibration
Verilog for Design and functional verification
Online Training in SystemVerilog for Functional Verification is structured to enable engineers to develop their skills in full breadth of systemverilog features. VT-SVO course covers all aspects of functional verification including constrained random verification, assertion based verification and coverage driven verification. VT-SVO course has been framed to fit to every functional verification engineer requirements and also targeted for graduates aspiring to make career in VLSI Front End domain. Course approaches by teaching basic concepts to most advanced aspects of SV with relevant examples to enable easier understanding of concepts.