ASIC n FPGA diff
DC transfer characteristics
second order effects
moore’s law: the count of transistor in the chip doubles every 18 months.
the manufacturing of transistors take place by semiconductors.
semiconductor device: due to the property of temperature.
[-40 to 125c]
si and ge
si – silicon is abundantly available , less cost
ge – more cost
si – add impurities to the si to make it work as conductor.
impurities – boron, phosphorus
diodes and transistors.
Diode: it is a two terminal device, the conduction takes places in only one direction.
Equilibrium – the state where the device
capacitor: the device which stores the charges.
why: to store the charge in the device.
calculate the cell delay.
1/ Cseries = [1/c1 + 1/c2]
Cparallel = [C1 + C2]
Qx = Cx. v
V1 = Q/c1.
Q = C.V C = e. A/d
ASIC: manufacture of ic for the partiular applications.
FPGA: manufacture of ic for any applications.
soc: integrating all the asic chip[semi custom chip] in only one chip.
ex: wifi , bluetooth, recording, tx/rx, storage.
transistor: three terminal semiconductor device using for manufacturing ic.
ex: BJT, MOSFET, FET, MESFET, JFET etc….
CMOS: the mosfet which is manufacturing using cmos technology.
why pmos is connected to vdd n nmos connected to vss?
– pmos passes strong 1[vdd], nmos passes strong 0[vss].
– if we reverse then it acts as buffer, after it reaches meta stability state.
meta stability: if device reaches this condition then , output cannot be
Realization of logic gates using cmos circuit.
‘.’ pmos are connected in parallel
‘.’ nmos are connected in series
why two inverters instead of buffer.
rise n fall time, and transition is more accurate in the case of inv.
why pmos size is greater than nmos?
pmos size is greater than nmos because mobility of electrons are greater than holes.
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