Session#1 (15/OCT)

Device fundamentals
ASIC n FPGA diff
CMOS fabrication
DC transfer characteristics
second order effects
double patterning
signal integrity
noise margin


moore’s law: the count of transistor in the chip doubles every 18 months.

the manufacturing of transistors take place by semiconductors.

semiconductor device: due to the property of temperature.
[-40 to 125c]

si and ge
si – silicon is abundantly available , less cost
ge – more cost

si – add impurities to the si to make it work as conductor.
impurities – boron, phosphorus

diodes and transistors.

Diode: it is a two terminal device, the conduction takes places in only one direction.
forward biased.
reverse biased.
Equilibrium – the state where the device
become saturation.


  1. electrical : R L C
  2. electronics: diodes and transitors.

different currents:

  1. drift current: – due to the applied energy or applied electric field, the drift current
  2. diffusion current: – due to the concentration gradient, diffusion current take place.

capacitor: the device which stores the charges.
why: to store the charge in the device.
calculate the cell delay.
1/ Cseries = [1/c1 + 1/c2]
Cparallel = [C1 + C2]
Qx = Cx. v
V1 = Q/c1.

Q = C.V C = e. A/d

  1. Q = C.V
    1. 8 = 80c
  2. Q = Cseries. v
    = (1/1 + 1/2 + 1/3). 8
    = 4.36c
    V1 = Q/C1 = 4.36/1 = 4.36V
    V2 = Q/C2 = 4.36/2 = 2.18V
    V3 = Q/C3 = 4.36/3 = 1.4533333V
    Q1 = C1.V =
    Q2 = C2.V
    Q3 = C3 .V
  3. Q = 12C
    Ceff = 3.3/(6) = 1.5v
    V1 =
    V2 =

V3 =

ASIC: manufacture of ic for the partiular applications.
FPGA: manufacture of ic for any applications.

  1. reconfigurable ckts 1. permanent
    [ only for one application] [ for many application]
  2. design using hdl, verilog 2. design using hdl, verilog
  3. not suited for high volume 3. used for mass production
  4. generally low frequency 4. high frequency
  5. analog devices are not suitable. 5. for analog devices fpga is best method.

6. less time to market 6. more time to market.


soc: integrating all the asic chip[semi custom chip] in only one chip.
ex: wifi , bluetooth, recording, tx/rx, storage.

transistor: three terminal semiconductor device using for manufacturing ic.


  1. what is bjt
  2. bjt CE, CB, CC configuration
  3. operation of bjt.

4. why always load is connected to capacitor.

CMOS: the mosfet which is manufacturing using cmos technology.

why pmos is connected to vdd n nmos connected to vss?
– pmos passes strong 1[vdd], nmos passes strong 0[vss].
– if we reverse then it acts as buffer, after it reaches meta stability state.
meta stability: if device reaches this condition then , output cannot be

Realization of logic gates using cmos circuit.

  1. nand : Y = ~[ A.B]

‘.’ pmos are connected in parallel
‘.’ nmos are connected in series

  1. nor : Y = ~[A+ B]
    ‘+’ pmos are connected in series
    ‘+’ nmos are connected in parallel.
  2. and n or gate

4. Y = ~((abc) + d)

why two inverters instead of buffer.
rise n fall time, and transition is more accurate in the case of inv.

why pmos size is greater than nmos?
pmos size is greater than nmos because mobility of electrons are greater than holes.
2:1[pmos: nmos].

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