SES#1

  1. Protocol?
    • various types of protocols?
    • how they are differentiated?
    • where does AXI fit in to?
  2. Important of AXI protocol?
  3. AXI protocol basics
  4. AXI signals
  5. AXI features
  6. AXI timing diagrams(write and read)

Course prerequisites:
– APB, SPI, I2C

  1. Protocol?
    o what is a protocol?
    – how address phase should happen?
    o what signals to be used?
    – how data phase should happen?
    – how response phase should happen?
  2. analogy
    o Bank
    o cash deposit
    o customer, cashier
    protocol for cash deposit:
    – fill the slip, account number, denominations, sign
    – issue this form to cashier ===> Request phase
    – cashier provides ACK(saying cash is deposited) ==> Response phase
    o cash deposit is a transaction
    o request phase + response phase ====> APB is suitable o same bank
    o home loan => does it get over in 10 minutes? 1 months.
    o home loan transaction has a longer process
    o application + documents multiple times + saction
    o application => address phase
    o documents submission => data phase
    o sanction => response phase
    o transaction = address phase + multiple data phases + response phase ==> AXI is suitable
  3. protocols
    o guidelines on communication between two components
    o one component: master
    o other component: slave
  4. this master and slave communication can be two types
    o onchip communication
    o both master and slave are present on same chip
    o peripheral communication
    o one component is present on one chip
    o other component is present on different chip
  5. Laptop
    o peripheral protocols?
    o anything we see coming outside laptop is peripheral communication
    o ex: USB, Ethernet, HDMI, PCIe, SDCARD, VGA, KBD
    o onchip protocols?
    o most of users will not be aware(these are internal to the chip)
    o AXI, AHB, APB, OCP
  6. onchip protocols are limited by frequency of operation
    o Laptop I am using is working at 2.5Ghz frequency
    o Processor inside my laptop is issuing trnasaction to other compoennts at 2.5GHz frequency
    o this communication happens through on chip protocols
    o this limitation is due to timing closure requirements.
    o Static timing analysis: setup and hold time closure for all the paths in the chip.
    o as we increase the chip frequency of operation, time period comes down, it becomes difficult to meet setup time.
  7. Current generation laptop => 3GHz
  8. PCIe protocol works at 32GT/s/lane (~32GHz)
    o communication is between one chip to anotehr chip
    o These high speed protocol use very specialized component called as “PHY”
  9. Get a feel of what is 32GT/s (32GHz)
    32102410241024 bits/second = 3210**9 = 3200 crores bits/second
  10. we want to purchase a mobile?
    o perofmrnace, features, power consumption, cost
    2K, 1L
  11. When we connect pendrive to laptop
    o data transfer happens in terms of USB frames(we don’t call as USB transactions)
  12. AXI
    o AXI transactions(we don’t call as AXI packets) packet/frame: series of bits
    transaction: individual fields(addr, data, burst_type, len, etc)
  13. AMBA protocols
  14. Post office does pincode decoding
    o 515.. => AP
    o 560.. => KTK

AXI communication:
o Address decoding

SES#2

  1. AXI is implemented using 5 channels
    o 3 write channels
    o 2 read channels
  2. Write tx
    o 1 write address phase (write address channel)
    o multiple write data phases (write data channel)
    o 1 write response phase (write response channel)
  3. APB signals start with p (paddr, pwdata, etc)
  4. AHB signals start with h
  5. AXI signals don’t start with a
  6. Why AXI is complicating the things, why 5 channels?
    • having 5 channels, makes it possible to do various(different) transactions at the same time.
  7. awburst =>
    bresp => write response
    rdata => read data channel
  8. How handshaking happens in AXI protocol?
  1. what happens if there is no handshaking implemented?
    o chance of losing the data
  2. awvalid : master
    awready : slave
    bvalid : slave
    o Slave is telling that, I am giving response information.
    bready : master
    o master is telling that, I am ready to accept the response information.
    wvalid : master
    wready : slave
  3. arvalid : master
    o master is telling to the slave, that, I want to read from you.
    arready: slave
    in response to above request from the master, slave will provide the read data. rvalid : slave
    rready : master
  4. To do a AXI write transaction, what signals are required.
    lets start with APB protocol:
    – pclk, prst, paddr, pwdata, prdata, pwrite, psel, penable, pready, perror most of these signals are also tehre in AXI protocol(with p changed)
    – aclk, arst
    write channel:
    awaddr,
    master needs to tell the slave, following information:
    – how many transfers I want to do?
    – how many bytes I will transfer each time?
    – what kind of transfer I will do?
    read channel:
    araddr
  5. Analogy
    I want to apply for a homeloan (home loan form: has an application number)
    I go to the bank.
    I fill the application => write address phase (1038438)
    o name, address, company, what all documents, how many docs ==> these details filled in applicaiton form
    I will start giving documents
    ID proof => 1st beat of write data phase
    – ID proof against above appliation number(1038438)
    address proof (appliation number: 1038438) burst length: how many documents I will be giving
    burst size: what is teh size of document I will be giving each time
    burst type: FIXED, INCR, WRAP
    ID : Identification signal write response phase (~sanction phase);
    saction to appliation number: 1038438
  1. Same concept in AXI is called as ‘ID’
    ID is 4 bit signal
    0 to 15

15.
awaddr = 32’h1000_0000
awlen = 5
awsize = 2
awburst = INCR
awid = 11
awlock = 2’b00
awvalid = 1 => master is telling to the slave that, I am giving valid infomraiton to you.
o please sample these signals
awready = 1 => captures all above signals
—— we completed with write address phase ———-

what will happen after this?
– write data phase.
– how many data phases will happen?
awlen + 1 = 6
– awsize = 2
2**awsize bytes per each transfer = 4
– awburst = INCR

1st data phase:
wid = 11
wdata = 32’h12345678 (any random data)
wstrb = 4’b1111
wlast = 0 => it will be 1 in last trnasfer
wvalid = 1
slave will drive, wready=1 indicating that, I am ready to accept your data

what slave will do with above data it received?
awaddr = 32’h1000_0000
at addr=32’h1000_0000, 8’h78
at addr=32’h1000_0001, 8’h56
at addr=32’h1000_0002, 8’h34
at addr=32’h1000_0003, 8’h12

2nd data phase: ==> it is called as trnasfer or beat
wid = 11
wdata = 32’h46478343;
wstrb = 4’b1111
wlast = 0 => it will be 1 in last trnasfer
wvalid = 1
slave will drive, wready=1 indicating that, I am ready to accept your data

what slave will do with above data it received?
at addr=32’h1000_0004, 8’h43
at addr=32’h1000_0005, 8’h83
at addr=32’h1000_0006, 8’h47
at addr=32’h1000_0007, 8’h46

3rd data phase:
wdata = 32’h46776343;
at addr=32’h1000_0008, 8’h43
at addr=32’h1000_0009, 8’h63
at addr=32’h1000_000a, 8’h77
at addr=32’h1000_000b, 8’h46

4th data phase:
wdata = 32’h67714252;
at addr=32’h1000_000c, 8’h52
at addr=32’h1000_000d, 8’h42
at addr=32’h1000_000e, 8’h71
at addr=32’h1000_000f, 8’h67

5th data phase:
32’h1000_0010 to 13

6th data phase: => last beat of the transaction
wdata = 32’h67714252;
wlast = 1 (indication to the slave that, it is last beat)

slave will store all this 6 data patterns (I have submitted 6 docuemtns to the bank)

Slave will give the response phase (~loan sanction)
o OKAY (loan is sanctioned)
o EXOKAY
o DECERR
o sending a post to a not existing pincode => dec error
o SLVERR
o

how slave will give response:
bid = 11
bresp = Okay
bvalid = 1
in response this, master will drive: bready = 1(I am ready to accept your response)
———————- COMPLTE WRITE TX IS DONE ————

32'h1000_0010 to 13

16Q. we are already having valid signal then why we use strobe?
wdata = 32’46478343;
wstrb = 4’b0011 ==> Narrow transfers
– only 43, 83 are only valid bytes => slave should store these two bytes only
– remaining two, it should ignore.

wvalid? => it is talking about whole data phase

  1. rresp = 2 bits
    2’b00 => OKAY response
    2’b01 => EXOKAY
    2’b10 => Decode error
    2’b11 => slave error

18.
AXI Read Transaction example:
Araddr = 32’h1000_F000
Arlen = 4
Arburst = Fixed
Arsize = 2

how many beats = 5
how many bytes per beat = 4
totally how many bytes in whole transaction = 5*4 = 20 bytes
master is requesting slave to give 20 bytes of data from the addr=32’h1000_F000

SES#3

  1. write transaction timing diagram
  2. read transaction timing diagram
  3. write channel signals
    o WA (AW)
    o WD (W)
    o WR (B)
  4. read channel signals
    o RA (AR)
    o RD (R)
  5. singifiance of all the signals
    o awaddr, awid, awlen, awburst, awsize, awvalid, awready
    o wdata, wstrb, wlast, wid, wvalid, wready
    o bresp, bid, bvalid, bready
  6. awburst
  7. took some transaction examples, understood how transfers happen
  8. how the handshaking happens, signal directions
  9. how ID signal makes various type of transactions posisble
    o out of order
    o overlapping
    o interleaved

Notes:

  1. awburst/arburst
    o 3 types: INCR(Incremneting), Wrapping, Fixed
    o when a processor or master generates a transaction(write or read), it checks what is the type of slave I am interacting with.
    o If slave if a FIFO => awburst = FIXED (awburst = 2’b00)
    o If slave if a memory => awburst = INCR (awburst = 2’b01)
    o If master is cache controller, which is accessing DDR memory => awburst = Wrap (awburst = 2’b10)
    o Cache controller needs to get data from the memory in boundary by boundary basis.
  2. how wrap and incr differ?
  3. wrap lower boundary = 32’h1000_0008
    wrap upper boundary = 32’h1000_001F
  4. narrow transfer
    o bus size = 32bits
    we are sending either 8 bits or 16 bits => narrow transfer => wstrb will be useful to decide which positions are valid.

5.
bus zie = 64 bits
what all bit trnasfers are possible under narrow transfer = 8(awsize=0), 16(awsize=1), 32(awsize=2)
64 bits: 8 bytes
awsize: 0(1 bytes), 1(21 : 2 bytes), 2(22 : 4 bytes)

  1. wrap calculation
    32’h100 => 256
    len = 4 => bursts = 5
    size = 1 => 2 bytes
    total tx size = 5*2 = 10 btyes
    boundaries: 0-9, 10-19, 20-29…

256%10 = 6
wrap lower addr = 256 – 6 = 250
32’h100 falls in to {32’hFA – 32’h103} boundary

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