SESSION#1

  1. AXI protocol is important
    o Qualcomm, Broadcom, NXP, ….
    o All these products are majorly based RISC architecture based processors.
    o ARM processor => Use eitehr AXI or AHB protocol as an interface
  2. AXI is among the complex on-chip protocols
    o If you know AXI, you can easily understand APB and AHB protocols.
  3. course
    o AXI protocol
    o AXI UVC using SV & UVM
  4. If AXI WDATA bus width is 32 bits (DW)
    how many clock cycles is required to transfer a total of 60 bytes?
    – 60 bytes => 15 DW’s
    – Each DW needs one clock cycle => 15 data transfer cycle
    – 1 address cycle
    – 1 response cycle
    – 17 clocks = 1 address + 15 data cycles + 1 response cycle how many clock cycles is required to transfer a total of 80 bytes? 22 cycles
  5. Bank homeloan
    o how much time totally taken to process a home loan? 1 month
    o home loan steps
    o applying for the loan => AXI protocol address phase
    o name or any other detals also?
    o not just name,
    o They assign an ‘application number’ for you
    o Document submission => AXI protocol data phases
    o submit salary proof, on that document you will write ‘application number’
    o address proof, on that document you will write ‘application number’
    o identity proof, on that document you will write ‘application number’

    o Sanction => AXI protocol response phase
    o Bank will sanction or reject => ‘application number’
  6. what if bank doesn’t use ‘application number’?
    o bank will get lot of documents => they will find it difficult to map with which application does this correspond to.
    o Without ‘application number’ => bank will be able to process only one home loan application at a time.
    o in 1 year => how many home loans they can process? 12
    o by using the ‘application number’ => now there is no limit on number of applications it can process.
  7. APB protocol
    • from APB protocol let us build AXI protocol.
    • APB protocol : pclk, prst, paddr, pwdata, prdata, psel, penable, pready, perror ===> One single channel
    • AHB protocol : hclk, hrst, haddr, hwdata, hrdata, htrans, hready, hresp, some other signals ===> One single channel
    • AXI protocol = APB protocol + Some new signals(specific to AXI advanced features) ===> 5 different channels
      o AXI divides all the signals in to 5 different channels
  8. Advantage of having 5 different channels.
    o analogy:
    – radio – AIR, 91.4, 98.3, 93.5, 94.5 => all of them able to transmit their signals independent of each other. => AXI
    – APB would be like => All above information will come in one channel => user don’t have option.
    o broadcaster will decide whether to send AIR or 91.4 or 98.3 or 93.5 or 94.5 => user has to listen o AXI
    o broadcaster sends all information in different channels => i can tune and listen what i need.
  9. AXI protocol instead of dealing all signals as one channel
    o all signals have been grouped in to 5 different channels.
  10. Write address phase (M->S)
    Write data phase (M->S)
    Write response phase (S->M)
  11. Read address phase (M->S)
    Read data phase (S->M)
    Read response phase (S->M)
    o AXI protocol developers merged both Read data and Read response phases in to single channel
    o Read data and response channel
  12. why AXI has 5 different channels?
    o 5 different channels helps with 5 independent transactions to happen on these channels at a given time.
    o Because of 5 different channels => Write and read transction can happen at same time.
  13. Does APB support concurrent write and read?
    • No
    • AHB also doesn’t support concurrent write and read => it do
  14. one AXI write tx
    o how many address transfers? 1
    o how many data transfers? multiple
    o how many response transfers? 1
  15. one AXI read tx
    o how many address transfers? 1
    o how many data transfers? multiple ==> Burst length
  16. How many bytes is transferred per beat?
    o burst size
  17. Entire thing => transaction
    o transaction = write_addr + multiple write_data + write_respnse
    o each write_data => transfer or beat
  18. AXI = APB + Burst_length + Burst_Size + …(later we will discuss)
  19. AXI = 5 channels
    write address => AW ==> awvalid(M), awready(S)
    o since all write address and control information is driven by master to the slave, awvalid is also given by master.
    o by driving awready=1, slave is telling that I am ready to accept the information.
    write data => W ==> wvalid(M), wready(S)
    write response => B ==> bvalid(S), bready(M)
    o write response is provided by slave => bvalid ? Slave
    read address => AR ==> arvalid(M), arready(S)
    read data => R ==> rvalid(S), rready(M)
  20. SInce above 5 channels are independent of each other => each of them have their own handshaking.
    o How handshaking works in APB protocol? penable and pready
    o master asserts(driving 1) penable to indicate that it wants to do a transfer
    o slave asserts pready(pready=1) to indicate that it is ready to complete the transfer o both penable=1 and pready=1 should happen at the postivie edge of the clock.

21.
awvalid => M
awready => S
wvalid => M
wready => S
= 30 minutes to memorize everything?? No
– sit for 2 hours => understand the logic(if you don’t understand talk to trainer)

22.
awaddr = 32’h100 (x100)
burst length = 4
burst size = 4 (4 bytes per beat)
total transaction size(total bytes in whole transaction) = 16 bytes

1st beat => 32’h12345678
2nd beat => 32’h1122334422.
awaddr = 32’h100 (x100)
burst length = 4
burst size = 4 (4 bytes per beat)
total transaction size(total bytes in whole transaction) = 16 bytes

1st beat => 32’h12345678
2nd beat => 32’h11223344
3rd beat => 32’h10203040
4th beat => 32’h38989434

to which address 98 will be written => 10E (Hexa)
to which address 20 will be written => 10A
to which address 44 will be written => 104
to which address 56 will be written => 101
o if you understand this => 50% of AXI protocol is complete

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