AHB Interconnect verification

Revision:

1. AHB UVC
   o Master UVC
   o SLave UVC
   o Validated master UVC by connecting to Slave UVC
   o we have developed various testcases focusing on different AHB features
   o testcases development is nothing but sequence development
   o also developed a scoreboard to check transactions at both master and slave interfaces
   o implement logic to check testcase pass/fail

Questions:

1. AHB interconnect
   o can be verified at 2 levels
   o standalone verification(IP verification, module level erification)
   We will develop testbench around AHB interconnect, we will mimick all the components around interconnect using AHB master/slave UVCs
   o chip level(SOC) verification
   We don’t need to keep any driver or sequencers around interconnect
   Processor, various other RTL blocks will be there, we just need to connect monitors at each of these interfaces.
   SOC level verification of AHB interconnect will only require monitor and scoreboard.
   IP level verification of AHB interconnect will only require monitor and scoreboard alongwith Master and Slave UVC of AHB.
2. You are in to SOC team, you are give AHB interconnect(fabric) verification
   project title: Chip level verification of AHB interconnect
3. You are in to IP team, you are give AHB interconnect(fabric) verification
   project title: Module level verification of AHB interconnect
4. uvm_config_db#(uvm_object_wrapper)::set(this, “env.ahb_env_i.agent.sqr.main_phase”, “default_sequence”, ahb_wr_rd_seq::get_type());
   ahb_wr_rd_seq should be run by env.ahb_env_i.agent.sqr in the main_phase.

• sequence has a keyword starting phase, that will be updated to main_phase
  user can raise and drop objections on starting_phase
  uvm1.1* version: starting_phase is a defualt keyword in every sequence
  uvm1.2* version: starting_phase is not availbel in sequence, we need to use get_starting_phase

Agenda:

1. AHB Interconnect
2. Testbench development
3. Sequence library
4. Virtual sequencer and virtual sequences
5. AHB Interconnect Testcases
6. Scoreboard

Notes:

1. AHB Interconnect helps connecting multiple masters to multiple slaves
   but when we are doing IP verification, we have to mimick the master/slave behavior, so we will be connecting UVC inplace of master/slaves.
2. what is teh issue without AHB Interconnect?
   o we will have establish many 1-1 connections
   if we have 4 masters, 3 slaves => then it will require 12 connections to be done
   AHB interconnect helps avoid this.

3.
Declaring array of physical interfaces is not possible
//ahb_intf mpif0(clk, rst) [2:0]; => syntax is it possible?
Declaring array of virtual interfaces is possible

4. When design architect develop the SOC architecture, he provides the memory map for the whole system
5. AHB-UVC
   copied it to AHB_IC_VERIFICATION
   • added ahb_ic.sv
     o coded 3 processes
     o arbitration
     o master-slave request/response routing
     o getting interface handles
   • updated ahb_env.sv
     o array of virtual interfaces: master and slave
   • added env configuration variables
     num_masters, num_slaves
     o whole TB is setup based on these two variables
   • we are checking the TB for 1 master and 1 slave configuration
     o if it works, then we will try for multiple masters and multiple slaves
6. Tx is showing on M0_VIF, but it is not showing on any of the slave interfaces
   o Address generated is targeting S0 => tx should appear on S0_VIF, which is not happening
   o where should we start debug?
   – forever blocks not put in fork join
7. Running test with 2 masters and 2 slaves
   o is the TB structure generated for 2 masters and 2 slaves? YES
   o why txs are not happening on mvif[1] => master1 is not generating any txs? WHY?
   o where to start debug?
   o debug always starts from test
   o Issue
   o there is no busreq happening on hbusreq[1]?
   o where to debug?
   o Master0, Master1 are doing the txs concurrently?
   o violation of AHB protocol
8. multiple masters, multiple slaves
   Issue:
   o master[0] : read data phase last data is missing
   o master[1] onwards : read data phase last 2 data are missing
   How to approach this debug?
   keep the problem simple
   1M, 1S TB setup
9. Sequence library

• keep all sequences in signle file
• register all(required) the sequences to be a library(of type uvm_sequence_library)
• user can create testcases using above seqeucne library(rather than using individual sequences)
  o why should user use sequence library instead of individual sequences?
  o it gives very interesting scenarios.
  o when we create test with all the seqeunces, it will run multiple sequences in the same test.
• till now, 1 test used to be mapped to one seqeunce
  o sequence library helps user run multuiple sequences in the same test.
• to use sequence library no need of coding any new sqeunces, existing sequences itself can be used to create new testcases.

4. by createing ahb_wrap_seq_lib and running test using this, we are doing STRESS TEST on wrap feature.
   • my test will generate 100’s of txs from different sequences which will be focuing only on wrap feature. Our idea, it may help us reach some corner wrap scenario, which we manually may not be able to get.
5. Sequence library

• OVM :
  o keeping all Sequences in a single file
• UVM :
  o create a class called sequence library, in to which all sequences are registered in to.
  o this sequence librayr is mapped to default_sequence of a sequencer, that way sequencer will run all the sequences of the library in different ways
  o RAND Mode
  o RANDC Mode
  o USER Mode
  o run only user defined sequence, not all sequences
  o Item Mode
  o pick one item from each sequence, do not run all items of a sqeuuence
  o User can also specify min_seq_count and max_seq_count to be run
  o user specifies this using uvm_sequence_library_cfg

4. Sequence library
   o defining library
   o one TB env can have multiple libraries
   o libraries are specific to one interface
   o we can’t merge sequences of diffeernt interfaces in to same library
   o adding sequences to the library
   o creating tests using library
   o understanding the benefits of library
5. Definining lirbary
   class ahb_seq_lib extends uvm_sequence_library#(ahb_tx); `uvm_object_utils(ahb_seq_lib) `uvm_sequence_library_utils(ahb_seq_lib) function new(string name=””); super.new(name); init_sequence_library(); endfunction

endclass

Important things:
`uvm_sequence_library_utils(ahb_seq_lib) //Setup library infrastructure
init_sequence_library(); //Initialize the library

14. adding sequences to the library

• list down seqeunces
  ahb_reset_seq
  ahb_configure_seq
  ahb_main_seq
  ahb_shutdown_seq
  ahb_item_seq
  ahb_intr_seq
  AMONG ABOVE SEQUENCES, WHICH SEQUENCES SHOULD BE PART OF LIBRARY
  `uvm_add_to_seq_lib(ahb_item_seq, ahb_seq_lib)
• seqeucnes can be diviedd in 4 categories
  o reset sequence
  o configure sequence
  o main seqeunce ====> library creation
  o intr service sqeuence

14. creating tests using library
    class ahb_seq_lib_test extends ahb_base_test;
    uvm_component_utils(ahb_seq_lib_test) NEW_COMP
    uvm_sequence_library_cfg seq_cfg;
    function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    seq_cfg = new(“seq_cfg”, UVM_SEQ_LIB_RAND, 5, 10);
    //pick 5 to 10 sequences from the library, run them in random order
    //run one after other
    uvm_config_db#(uvm_object_wrapper)::set(this, “env.magent.sqr.run_phase”, “default_sequence”, ahb_seq_lib::get_type());
    uvm_config_db#(uvm_object_wrapper)::set(this, “env.magent.sqr.run_phase”, “default_sequence.config”, seq_cfg);
    endfunction
    endclass
15. Benefit of library

• user can create random sequences with minimal effort
• it will help reach corner case scenarios easily
• this is done towards end of the project
  o Do not group all sequences in to single library
  o project may have 5 libraries
  o apb_seq_lib
  o ahb_main-seq_lib
  o pcie_seq_lib

14. Important part of sequence library
    • how many libraries do we need in this project?
    • what all sequences should be part of the library?
    • Sequence library should not be learnt just for inerview purpose
      o HOW CAN MAKE SURE OF SEQEUNCE LIBRARY TO CREATE SOME INTERESTING TESTCASES.

AHB Interconnect scoreboard

Revision:

1. sequence library
   o typically testcases are targeted on feature basis
   o sequence library helps maps all the specific feature targeted tests to single library
   o user can develop tests using this feature_speciifc_library
   o it provides with option to stress test the specific feature
   o Similar to this, we can create multiple libraries each targeting speicifc feature and run testcases targeting each feature.
   o libraries are used towards the end of the project.
   o we use exisitng sequences to create complex testcases.
2. sequence library
   o how to define library?
   o how to add sequences to library?
   o how to create tests using library?
3. scoreboard

Agenda:

• AHB I/C feature listing down and testcases
• Scoreboard
• Virtual sequencer and virtual sequences
  • APB agent coding
• Different styles of sequence coding
• Different types of sequences

Questions:

1. Bufferable transactions

• Processor issues write transaction
  o interconnect gives the response to the transaction. It further completes the transaction.
  o Processor gets the response with lower latency, hence it can initiate a new request without wiating for write to happen to actual slave.
  o Bufferable transactions improves the transaction efficiency.

1. HSPLIT[1] = 1 => if it is given SLave#3
   o SLave#3 is indicating earlier I had split a transaction from Master#1, now I am ready to respond to Master#1.
   o HSPLIT is a signal going from Slave to Arbiter(not master), indicating slave readiness to responsd to specific master.
   o Arbiter takes in to account this signal value as part of arbitration scheme.
   o whenever it sees that a slave it ready to respond to master#1, it brings in master#1 to arbitration scheme.
   o if master#1 gets the grant now, it does INCR and completes the pending transaction.

Notes:

1. AHB I/C feature listing down and testcases
   configurable number of master, slaves
   1M-1S
   maximum supported masters and slaves
   Split, retry
   Connect split capable slaves (SPLIT)
   Split high priority master tx
   Split low priority master tx
   Connect split non-capable slaves (RETRY)
   Retry high priority master tx
   Retry low priority master tx
   Early burst termination
   EBT while locked transfer is happening
   EBT while unlocked transfer is happening
   high priority master
   low priority master
   protected transfers
   try different possible hprot values
   Locked transfers
   checked as part of EBT
   Different burst types
   Wrap
   Incr
   Single
   INCR with undefined length
   priority configuration
   Configure design for different possible priority values to masters
   Error scenarios
   targeting non existing address/slave
   Doing a normal access to a privileged slave
   Doing unaligned transfer
   Doing transfers that violate AHB protocol
   boundary of 2KB
   Transaction size more than 1KB
   corner case scenarios
   Particular Slave splitting all masters
   High priority master transaction is retry and slave is not able to complete the response tx for this.
2. uvm_in_order_comparator

• in built uvm_component based class, used for comparison of tranascations coming from 2 different ports, one port called as before_export and otehr port is called as after_export

1. virtual sequencer
   analogy:
   VLSI design flow execution
   RTL Design : manager#1
   Functional verification : manager#2
   PnR flow : manager#3
   Custom layout : manager#4
   Program manager => like virtual sequencer
   o has access to all teh manager
   o he does not execute any of the VLSI design flow aspects himself
   o he makes sure that there is order in project execution, he will take care of any synchronization between different teams

Project#1:
o manager#1 should do project#1.RTL_Design from this time to this time
o manager#2 should do project#1.RTL_verification from this time to this time
o manager#3 should do project#1.PnR from this time to this time
o manager#4 should do project#1.Custom layout from this time to this time

whatever scheudle program manager comes up with is the virtual sequence.

4. AHB I/C : to implement virtual seqeunce and seqeuncer, we need APB interface and APB agent coding