• Duration: 30 weeks (8 months)
• Phase#1 – 3 months
• Advanced Digital design
• GVIM text editor, Linux basics commands
• Verilog
• Phase#2 – 2.5 months
• System Verilog
• UVM
• Linux commands – hands on
• Soft skill training – regular weekly sessions
• Candidate gets placement support after 5.5 months of training, i.e after phase#2
• Phase#3 – 2.5 months
• AXI protocol and TB development
• Ethernet MAC core verification using SV & UVM
• Python
• ASIC flow and SOC verification concepts
• RISC-V based SV Verification project

Combinational logic

• Number systems
• Radix conversions
• K-maps, min-terms, max terms
• Logic gates
• Realization of logic gates using mux's and universal gates
• Compliments (1/2/9/10's complement)
• Arithmetic operations using compliments
• Boolean expression minimization, Dmorgan theorems
• POS and SOP
• Conversion and realization
• Adders
• Half adder
• Full adder
• Subtractor
• Half subtractor
• Full subtractor
• Multiplexers
• Realizing bigger Mux's using smaller Mux's
• Implementing Adders and subtractors using Multiplexers
• Decoders and Encoders
• Implementing Decoders and Encoders using Mux and Demux
• Bigger Decoder/Encoder using smaller Decoder/Encoder
• Comparators
• Implementing multi bit Comparators using 1-bit Comparator

Sequential logic

• Latch, Flipflop
• Latch, Flipflop using Gates or Mux's
• Different types of FFs
• FF Truth table
• Excitation tables
• Realization of FF's using other FF's
• Applications of FF's, Latches
• Counters
• Shift registers
• Synchronizers for clock domain crossing
• FSM's
• Mealy, Moore FSM
• Different encoding styles
• Frequency dividers
• Frequency multiplication
• STA
• Setup time, Hold time, timing closure
• fixing setup time and hold time violations
• Launch flop, capture flop

• Verilog language basics
• Verilog : How the language evolved?
• Verilog execution using Modelsim
• Verilog constructs
• Literals
• Data types
• registers, nets
• Vectors, Array
• Operators
• Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
• Continuous assignments
• Combinational logic coding : Half adder, full adder, multiplexer, comparator, encoder, decoder, priority encoder
• Generate
• Procedural timing controls
• task and functions
• system task and function
• modeling memories and FSM
• Parameters
• Port connections
• Procedural blocks
• Sensitivity list
• State machines
• timescale
• Verilog timing regions
• process
• Blocking and nonblocking statements
• Inferring combinational and Sequential logic
• Clock generation with Duty cycle & Jitter
• Shift register implementation
• Procedural Blocks
• fork join
• Race conditions
• Synthesis examples
• Inter and Intra delay statements
• example to showcase race condition using blocking assignments
• Pipelining
• Memories
• Structural modeling
• Verilog Programming Interface(& PLI)
• PLI
• compiler directives
• system task usage: $display, $monitor, $strobe
• PLI, VPI implementation
• Primitive implementation using table, endtable

• DFF coding using gate level, behavioral
• Counters
• Up counter
• Ring counter
• Johnson counter
• Memory RTL coding and TB development
• Memory Verilog coding
• Declaring a parameterized memory
• Front door access
• Back door access test case coding
• Implementing task for front door and back door access
• Test case coding and understanding waveforms
• FIFO – Synchronous FIFO and Asynchronous FIFO
• Synchronous FIFO
• Asynchronous FIFO
• Finite state machines
• Mealy and Moore style
• Implicit and Explicit styles of coding
• Pattern detector – Overlapping, Non-Overlapping, Dynamic
• Overlapping
• Non-Overlapping
• Dynamic
• Traffic light controller
• APB protocol
• Interrupt controller
• SPI controller
• CRC generation

• Functional Verification overview
• Test bench architecture
• Test bench components
• Test bench development : Modularity, Reusability
• Understanding Functional Verification flow
• System Verilog Course overview
• System Verilog language features
• Verilog for TB development
• Verilog Language constructs and shortcomings
• operators, data types
• Literals
• Operators - How things change from Verilog
• Data types - Integer based, string
• Arrays
• Arrays
• Array classification
• Packed and Unpacked Arrays
• Static and Dynamic Arrays
• Multi dimensional Arrays
• Dynamic Arrays
• Associative Arrays
• Queue
• Array of Queues in scoreboard implementation, other complex declarations
• Object Oriented Programming
• Basics of OOP – Class, Object, handle
• Class elements – Properties, methods, constraints
• Properties – 5 attributes in property declaration – rand/randc, signed, static, 2/4 state, data hiding
• Language provided and User defined methods
• Developing Ethernet frame and APB Tx class
• new constructor
• randomize, pre_randomize, post_randomize
• User defined methods – print, copy, compare, pack, unpack
• Encapsulation – Data hiding, local, protected, public
• Inheritance
• Ethernet frame generation example to learn OOP
• Polymorphism – real life usecases
• this, super
• Class forward declaration
• Multiple levels of inheritance
• Abstract class
• Parameterized classes
• Difference from Verilog parameterization
• Parameterization with inheritance – 4 combinations
• Parameterized classes for testbench development
• Static properties and methods
• Interface class
• Constant class property
• Scope resolution operator
• Nested class
• Variable scope
• Object copying – copy by handle, shallow copy, deep copy
• $cast – static and dynamic casting
• Advanced Data types
• Data types – Chandle, event, typedef, struct, union, enum
• Using struct data type for medals tally sorting example
• Typedef for defining complex data types
• Using complex data types in scoreboard development
• Fork join, Inter process synchronization
• Labeling
• Fork join – join_any, join, join_none
• Nested fork
• Labeling fork
• Process, process states
• Inter process synchronization
• IPS constructs – mailbox, event, Semaphore
• mailbox – types, methods
• events – persistant, synchronization examples
• Semaphore – synchronization examples
• Project to learn all SV language constructs
• Project – Memory TB development covering 90% of SV language constructs
• Configurable memory TB development
• Interface – Ports, internal signals, clocking block, modport
• using clocking block to fix design - TB synchronization issues
• Physical interface, virtual interface
• Using interface for design and TB connection
• Program
• Program significance
• How Program differs from Module
• Why Program is redundant?
• Scheduling semantics
• Scheduling semantics
• Task, Function
• Task, function – how they are different from Verilog
• Static & automatic task/functions
• System task and functions
• Constraints, Randomization
• Constraints format
• Constraints type – Simple, distribution, implication, if-else, iterative, variable ordering, soft, unique
• Inline constraints
• Constraints for queue randomization
• Constraints virtual nature
• Randomization
• randcase
• Randomization in class, module
• rand, randc
• Constrained random verification
• Directed verification
• Multiple hands on examples on Constraints and Randomization
• Chip select example using multiple inter related constraints
• new significance for randc
• Functional and code coverage
• Functional Coverage
• What is functional coverage?
• Need for functional coverage
• Where FC comes in functional verification flow?
• How to implement FC?
• Different types of FC?
• Integrating Functional coverage in Test bench
• functional coverage hierarchy
• Different types of coverpoints – simple, cross, transition
• Different types of bins – normal, illegal, ignore
• coverage calculation
• coverage options – auto_bin_max, weight, at_least, goal, comment, name, per_instance, detect_overlap
• Listing down cover points for a design
• Instance coverage
• Cross coverage with intersect
• FC system task & Functions
• Coverage Driven Verification
• Coverage report analysis
• Cover groups with arguments
• Coverage filter using iff
• Functional coverage types in TB – transaction class coverage, register field coverage, scenario coverage
• Code coverage
• Generating code coverage
• Different types of code coverage – FSM, Conditional, Branch, Expression, Statement, Toggle
• Detailed understanding of code coverage types with examples
• Merging UCDBs, generating coverage reports
• Analyzing coverage report
• Coverage exclusion
• Assertions and Assertion based verification
• Need for assertions?
• Assertion based verification
• Types of assertions
• Immediate assertions
• Concurrent assertions
• Assertion format – antecedent, consequent
• Running assertions using questasim, debugging the assertions in waveform
• Assertion hierarchy – property, sequence, boolean expression
• ##, |-> and |=> operators
• Assertion examples for clock frequency check
• Assertion with local variables
• Assertions for simple timing diagrams
• Listing down and implementing assertions for simple designs – Async FIFO, Interrupt controller
• DPI
• Direct Programming Interface(DPI)
• import and export of functions
• Configuration libraries, Packages, XMR
• Configuration Libraries
• Incremental compilation
• Packages – defining, importing
• XMR
• Configuration libraries, Packages, XMR
• Compiler directives & Macros
• Parameterizable macros
• VCD – value change dump
• common array methods
• Callbacks – multiple use case examples

• What is UVM? Need for a methodology?
• How UVM evolved?
• OVM, AVM, RVM, NVM, eRM
• UVM class library
• Classification of base classes in various categories
• OOP basics
• Encapsulation
• Inheritance
• Polymorphism
• Parameterized classes
• Parameterized macros
• Static properties and static methods
• Abstract classes
• Pure virtual methods
• How above aspect correlates with UVM implementation.
• UVM Class Library, Macros, Utilities
• Detailed overview of important UVM base classes, Macros and Utility classes.
• UVM TB Architecture
• Setting up a UVM based testbench for APB protocol from scratch.
• Significance of uvm_root in UVM based testbenches.
• run_test, how it starts whole TB flow.
• Command line processor
• Reporting classes
• Uvm_report_object
• Uvm_report_handler
• Uvm_report_server
• Detailed examples on use of methods in these classes.
• Objections
• UVM Factory
• Configuration DB, Resource DB
• Detailed usage of both data bases.
• How config_db is related to resource_db?
• Using config_db to change the testbench architecture.
• TLM1.0
• Push
• Pull
• FIFO
• Analysis
• Complex example on AHB to AXI transaction conversion.
• Simulation Phases
• UVM common phases
• Scheduled phases
• Sequences, Sequencers
• Default sequence
• p_sequencer
• m_sequencer
• Test case development
• Different styles of mapping testcase to sequence
• Using default sequence and scheduled phases
• Using sequence start method
• Configuring TB Environment
• Advanced aspects of developing a highly configurable test bench environment.
• Concept of knobs of test case scenario generation
• Using top level parameters to control the overall TB architecture
• Different testbench component coding
• Monitor
• Coverage
• Scoreboard
• Checkers
• Assertions
• Different styles of sequence development
• `uvm_do
• start_item and finish_item
• Using existing sequences
• Sequence library
• Creating complex test cases using sequence library
• Virtual Sequencer, Virtual sequences

• Installing Linux platform in Windows
• Linux basics
• Linux versus Windows
• Linux Terminal
• File and Directory management
• Changing file permissions
• Absolute path and relative path
• Working with directories
• GVIM – major keyboard shortcuts
• Text display commands
• Root configuration files
• Environment variables
• Text processing commands
• grep, fgrep
• xargs
• SEd
• AWK
• Pipes and filters
• Connecting to server
• Process management
• LSF
• Ping
• FTP
• CTAGs
• File compress and extract
• Soft links

• Protocol basics
• Protocol overview
• Protocol features
• AMBA protocol overview
• AXI Protocol basics
• SOC Architecture – Significance of AXI protocol
• AXI based system architecture
• Correlating AXI with APB protocol
• Ports(signals) required for AXI protocol
• AXI Channels
• Write & Read Channels
• Handshaking using valid and ready
• Write Channel Signals – Address, Data and Response
• Read Channel Signals – Address and Data
• Timing diagrams
• How to draw the timing diagrams?
• Write Transaction Timing Diagram
• Read Transaction Timing Diagram
• AXI transaction analysis for big endian and little endian architecture
• Wrap transactions – write and read
• Narrow transfers
• Data bus and strobe relation
• Aligned and unaligned transfers
• AXI signal encoding
• Responses in AXI
• Locked and exclusive transfers
• Overlapping, out of order, interleaved txs
• Interconnect role in out of order transaction
• Significance of ID in AXI protocol
• AXI Channel handshake dependency
• Cacheable and bufferable transactions
• Protected transactions
• AXI VIP and UVC development
• Need for UVC?
• Different types of UVC's
• UVC usage in module and SOC verification
• Where Passive UVC are used?
• UVC integration in to TB
• AXI UVC architecture
• AXI Transaction Definition
• AXI UVC coding
• AXI TB simulation and wave form analysis
• AXI UVC integration
• AXI scoreboard coding

• SoC Verification Concepts
• Module Level Verification
• Constrained Random Verification
• Coverage Driven Verification
• Directed Verification
• Assertion Based Verification

• Reading design specification
• How to read specification – understanding architecture, sub blocks, interfaces, registers
• Listing down features, scenarios
• Develop testplan
• Functional coverage point list down
• Develop Testbench architecture
• Testbench component coding and integration
• Develop sanity testcases(smoke tests)
• Bring up test bench environment using sanity testcases
• Develop rest of test bench components including monitor, coverage and scoreboard
• Register model(RAL) development and integration
• Register write-read, reset tests using front door and back door access
• Functional testcase coding using Register model
• Functional testcase debug using RTL, data flow and schematic tracing
• Setup regression using Python
• Debug regression failures
• Functional, Code and assertion coverage analysis
• Develop more functional tests for coverage improvement

• Schematic tracing
• RTL tracing
• Fixing RTL and TB syntax and logical errors

• SOC Architecture overview
• SOC verification concepts
• SOC Components
• SOC use cases
• SOC Testbench architecture
• SOC verification differences with module verification

• Specification
• RTL coding, lint checks
• RTL integration
• Connectivity checks
• Functional Verification
• Synthesis & STA
• Gate level simulations
• Power aware simulations
• Placement and Routing
• DFT
• Custom layout
• Post silicon validation

• Python Interpreter
• Variables
• File management
• Subroutines
• Regular expressions
• Object oriented Python
• Python modules

• Facing interviews effectively
• industry work culture
• Group discussions

100+ detailed assignments covering all aspects from Verilog, Advanced digital design, System verilog, UVM, AXI protocol, VIP Development, Ethernet MAC core verification, RTL debug, UNIX and PERL scripting.