- Functional Verification overview
- Test bench architecture
- Test bench components
- Test bench development : Modularity, Reusability
- Understanding Functional Verification flow
- System Verilog Course overview
- System Verilog language features
- Verilog for TB development
- Verilog Language constructs and shortcomings
- operators, data types
- Literals
- Operators – How things change from Verilog
- Data types – Integer based, string
- Arrays
- Arrays
- Array classification
- Packed and Unpacked Arrays
- Static and Dynamic Arrays
- Multi dimensional Arrays
- Dynamic Arrays
- Associative Arrays
- Queue
- Array of Queues in scoreboard implementation, other complex declarations
- Object Oriented Programming
- Basics of OOP – Class, Object, handle
- Class elements – Properties, methods, constraints
- Properties – 5 attributes in property declaration – rand/randc, signed, static, 2/4 state, data hiding
- Language provided and User defined methods
- Developing Ethernet frame and APB Tx class
- new constructor
- randomize, pre_randomize, post_randomize
- User defined methods – print, copy, compare, pack, unpack
- Encapsulation – Data hiding, local, protected, public
- Inheritance
- Ethernet frame generation example to learn OOP
- Polymorphism – real life usecases
- this, super
- Class forward declaration
- Multiple levels of inheritance
- Abstract class
- Parameterized classes
- Difference from Verilog parameterization
- Parameterization with inheritance – 4 combinations
- Parameterized classes for testbench development
- Static properties and methods
- Interface class
- Constant class property
- Scope resolution operator
- Nested class
- Variable scope
- Object copying – copy by handle, shallow copy, deep copy
- $cast – static and dynamic casting
- Advanced Data types
- Data types – Chandle, event, typedef, struct, union, enum
- Using struct data type for medals tally sorting example
- Typedef for defining complex data types
- Using complex data types in scoreboard development
- Fork join, Inter process synchronization
- Labeling
- Fork join – join_any, join, join_none
- Nested fork
- Labeling fork
- Process, process states
- Inter process synchronization
- IPS constructs – mailbox, event, Semaphore
- mailbox – types, methods
- events – persistant, synchronization examples
- Semaphore – synchronization examples
- Project to learn all SV language constructs
- Project – Memory TB development covering 90% of SV language constructs
- Configurable memory TB development
- Interface – Ports, internal signals, clocking block, modport
- using clocking block to fix design – TB synchronization issues
- Physical interface, virtual interface
- Using interface for design and TB connection
- Program
- Program significance
- How Program differs from Module
- Why Program is redundant?
- Scheduling semantics
- Task, Function
- Task, function – how they are different from Verilog
- Static & automatic task/functions
- System task and functions
- Constraints, Randomization
- Constraints format
- Constraints type – Simple, distribution, implication, if-else, iterative, variable ordering, soft, unique
- Inline constraints
- Constraints for queue randomization
- Constraints virtual nature
- Randomization
- randcase
- Randomization in class, module
- rand, randc
- Constrained random verification
- Directed verification
- Multiple hands on examples on Constraints and Randomization
- Chip select example using multiple inter related constraints
- new significance for randc
- Functional and code coverage
- Functional Coverage
- What is functional coverage?
- Need for functional coverage
- Where FC comes in functional verification flow?
- How to implement FC?
- Different types of FC?
- Integrating Functional coverage in Test bench
- functional coverage hierarchy
- Different types of coverpoints – simple, cross, transition
- Different types of bins – normal, illegal, ignore
- coverage calculation
- coverage options – auto_bin_max, weigth, at_least, goal, comment, name, per_instance, detect_overlap
- Listing down cover points for a design
- Instance coverage
- Cross coverage with intersect
- FC system task & Functions
- Coverage Driven Verification
- Coverage report analysis
- Cover groups with arguments
- Coverage filter using iff
- Functional coverage types in TB – transaction class coverage, register field coverage, scenario coverage
- Code coverage
- Generating code coverage
- Different types of code coverage – FSM, Conditional, Branch, Expression, Statement, Toggle
- Detailed understanding of code coverage types with examples
- Merging UCDBs, generating coverage reports
- Analyzing coverage report
- Coverage exclusion
- Assertions and Assertion based verification
- Need for assertions?
- Assertion based verification
- Types of assertions
- Immediate assertions
- Concurrent assertions
- Assertion format – antecedent, consequent
- Running assertions using questasim, debugging the assertions in waveform
- Assertion hierarchy – property, sequence, boolean expression
- ##, |-> and |=> operators
- Assertion examples for clock frequency check
- Assertion with local variables
- Assertions for simple timing diagrams
- Listing down and implmeneting assertions for simple designs – Async FIFO, Interrupt controller
- DPI
- Direct Programming Interface(DPI)
- import and export of functions
- Configuration libraries, Packages, XMR
- Configuration Libraries
- Incremental compilation
- Packages – defining, importing
- XMR
- Configuration libraries, Packages, XMR
- Compiler directives & Macros
- Parameterizable macros
- VCD – value change dump
- common array methods
- Callbacks – multiple use case examples
- Protocol basics
- Protocol overview
- Protocol features
- AMBA protocol overview
- AXI Protocol basics
- SOC Architecture – Significance of AXI protocol
- AXI based system architecture
- Correlating AXI with APB protocol
- Ports(signals) required for AXI protocol
- AXI Channels
- Write & Read Channels
- Handshaking using valid and ready
- Write Channel Signals – Address, Data and Response
- Read Channel Signals – Address and Data
- Timing diagrams
- How to draw the timing diagrams?
- Write Transaction Timing Diagram
- Read Transaction Timing Diagram
- AXI transaction analysis for big endian and little endian architecture
- Wrap transactions – write and read
- Narrow transfers
- Data bus and strobe relation
- Aligned and unaligned transfers
- AXI signal encoding
- Responses in AXI
- Locked and exclusive transfers
- Overlapping, out of order, interleaved txs
- Interconnect role in out of order transaction
- Significance of ID in AXI protocol
- AXI Channel handshake dependency
- Cacheable and bufferable transactions
- Protected transactions
- AXI VIP and UVC development
- Need for UVC?
- Different types of UVC’s
- UVC usage in module and SOC verification
- Where Passive UVC are used?
- UVC integration in to TB
- AXI UVC architecture
- AXI Transaction Definition
- AXI UVC coding
- AXI TB simulation and wave form analysis
- AXI UVC integration
- AXI scoreboard coding – Out of order tx handling
- Reading Specification
- Feature listing down
- Scenario Listing down
- Functional coverage listing down
- Coverage Implementation
- Testplan creation
- Testbench architecture development
- Testbench component coding
- Testcase coding and debug
- Assertions coding
- Regression setup
- Regression debug
- Verification closure
- Regression closure
- Functional & Code coverage closure
- SoC Verification Concepts
- Module Level Verification
- Constrained Random Verification
- Coverage Driven Verification
- Directed Verification
- Assertion Based Verification
- Reading design specification
- How to read specification – understanding architecture, sub blocks, interfaces, registers
- Listing down features, scenarios
- Develop testplan
- Functional coverage point list down
- Develop Testbench architecture
- Testbench component coding and integration
- Develop sanity testcases(smoke tests)
- Bring up test bench environment using sanity testcases
- Develop rest of test bench components including monitor, coverage and scoreboard
- Register model(RAL) development and integration
- Register write-read, reset tests using front door and back door access
- Functional testcase coding using Register model
- Functional testcase debug using RTL, data flow and schematic tracing
- Setup regression using Python
- Debug regression failures
- Functional, Code and assertion coverage analysis
- Develop more functional tests for coverage improvement
- Introduction to Python
- What is Python?
- Python Scripts
- Print Functions
- Literals
- Quoting Rules
- Fundamentals of Python
- Numbers and Strings
- Lists and Tuples
- Dictionary
- Standard Input and Output
- Predefined file Handles
- Operators and Conditions
- String, Assignment, Arithmetic Operators
- Relational and Equality Operators
- Logical operators
- Regular Expressions
- Simple Statements and Modifies
- Pattern Matching
- The tr function
- Pattern Matching
- Loops
- Labels and Blocks
- While, Until, For
- Labels, Loops and loop control
- Foreach
- Working with Files
- User Defined file handles
- Open file for Writing, Reading, Appending
- Open for pipes
- Close, eof functions
- Arguments
- @ARGV array command line arguments
- ARGV and the Shift functions
- Array Built-in Functions
- Functions: grep, split, join, slice, pop, push
- Functions: shift, unshift, reverse, sort, chop, chomp
- Associative Array Functions
- Python Modules
- Subroutines
- Passing by reference, value
- Return statement
- Standard Perl Library
- @INC Array
- Packages and .pl files
- Require function
- Modules and .pm Files
- Objects and Object Oriented Python
- Object oriented Python
- Classes
- my function
- objects, methods
- destructors
- Inheritance
- Derives classes
- Python for VLSI flow automation
- Setting up complete regression flow till report generation
- Creating complete SOC Test bench Environment Structure
- Developing test cases using parameter input text file
- CSV file handling
- Generating testbench using CSV file and user provided input
- Handling regression logs
- Parsing spreadsheet and writing spreadsheet.
- UVM Register Model Creation using spreadsheet
- Regression result speadsheet creation
- Regression result HTML creation
- Recursive directory manipulation
40+ detailed assignments covering all aspects of SV & UVM.
Below is the list of projects student will be doing as part of 26 weeks training. Institute provides guidance(trainer doing all projects from scratch) on all these projects. If student gains expertise in these projects, learning will be on-par with a 2 to 3 years experienced engineer. By working on below projects, student will get familiar with:
- majority of standard protocols(AXI, AHB, APB, SDRAM, Ethernet, etc)
- Industry standard simulation tools like Questasim & VCS
- RTL debug expertise
- RTL coding and TB development
Ethernet MAC is MAC core with transmit and receive logic working at 100Mbps. Design consists of five sub modules including DMA controller, MII, transmit, receive and control module. Course also covers the MAC 802.3 protocol standard.
This project provides student with detailed exposure to complete functional verification flow starting from reading the specification till coverage report generation and regression analysis. Student will get exposure to regression setup, coverage analysis and scoreboard development. This project is also good for working professionals whose work is generally confined to limited aspects of verification flow and want to get quick hands on exposure to complete flow.
What student learns from this project:
- Understand various 802 standards and more specifically 802.3 standard
- Understand various layers in OSI reference model and significance of network layer and MAC layer.
- Understand the whole process of functional verification flow starting from Specification to coverage analysis and closure.
- Ethernet MAC Specification detailed overview
- Design specification
- Listing down features, scenarios
- Developing testplan
- Testbench architecture
- Testbench component coding
- Functional coverage coding
- Register model coding and integration
- Assertion development
- Testbench component integration
- Sanity Testcase coding
- Functional Testcase coding
- Regression setup using Python
- Regression debug
- coverage report generation and analysis
AXI3.0 is an AMBA protocol used for high performance applications. AXI3.0 supports various features like out of order transactions, burst transfers, cacheble and bufferable transactions few among various features supported.
VIP was developed to work as both master and slave. Developed all the VIP components and validated VIP for various AXI features.
What student learns from this project:
- Develop VIP Architecture to be compatible with both master and slave behavior
- List down AXI features and develop testplan for validating AHB VIP
- Develop AXI VIP components
- Integrated AXI Master VIP with slave VIP
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of VIP validation using coverage criteria
AHB2.0 is an AMBA protocol used for medium performance applications. I was part of UVC development team. UVC was developed to work as both master and slave. Developed all the UVC components and validated UVC for various AHB features.
What student learns in this project:
- Develop UVC Architecture to be compatible with both master and slave behavior
- List down AHB features and develop testplan for validating AHB UVC
- Develop AHB UVC components
- Integrated AHB Master UVC with slave UVC
- Develop sanity testcases and debug the same
- Develop functional tests and debug the same
- Regression setup and closing of UVC validation using coverage criteria
FIFO is a design block used for connecting components working at either same or different frequencies. This project covers all the UVM TB setup for asynchronous FIFO. This project is focused on teaching UVM constructs from practical usage perspective.
What student learns in this project:
- Understand how to setup UVM TB for a design with 2 master interface
- Get hands on exposure to all UVM constructs
- Listing down features, scenarios – useful for interviews
- Develop test bench architecture using virtual sequencer
- Develop write and read interface agents
- Integrate both agents to the test bench
- Implement various test cases
- How to use virtual sequencer and virtual sequences in test case coding
- Regression setup and coverage analysis
AHB Interconnect is a design with configurable number of masters and slave interfaces. Design has an arbiter to route the master AHB transactions to corresponding slaves.
What student learns in this project:
- Listing down features, scenarios for a given design
- Developing test plan
- Develop TB architecture
- Integrate AHB Master UVC and AHB slave UVC in setting up AHB I/C TB
- Develop sanity testcases and debug
- Develop functional tests and debug
- Regression setup and coverage analysis
USB2.0 core is a design used for interfacing USB device with the USB host. USB2.0 core has three interfaces, one for UTMI interfacing, second for functional controller interfacing and third for buffer memory. USB2.0 design has 69 registers for configuration USB core behaviour including Endpoints.
What student learns in this project:
- Listing down registers, fields, their attributes
- Develop register model using UVM Register base classes
- Integrate in USB core TB
- Run register write read and reset testcases
