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UVM discussion forum

Guidelines: Please post queries from UVM course; this will be a common platform for posting all UVM queries. Queries related to UVM language constructs, UVC Development, TB Component coding. Queries will be answered by both trainers and students. Same page will be used for all...
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Systemverilog discussion forum

Guidelines: Please post queries from Systemverilog course; this will be a common platform for posting all SV queries. Queries related to SV language constructs, VIP Development, TB Component coding. Queries will be answered by both trainers and students. Same page will be used...
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UVM

Please post your UVM queries below. Trainer will address queries on priority.
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AMBA4 APB UVC Development

VIP & UVC development for AMBA Protocols: AMBA : Advanced Microcontroller Bus Architecture AMBA protocols come in various generations, targeted for various data through put requirements. Consists of following protocols (Starting from least complex to most complex) APB :...
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System Verilog Functional Coverage implementation in testbench

  Functional Coverage for AXI Interface Signals Functional verification comprises a large portion of the resources required to design and validate a complexsystem. Often, the validation must be comprehensive without redundant effort. To minimize wasted effort,coverage is...
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Clocking blocks in SystemVerilog_vlsi

Clocking blocks in SystemVerilog

Clocking blocks in SystemVerilog     We will discuss following: — Clocking block declarations — Input and output skews — Clocking block signal events — Cycle delays — Synchronous events — Synchronous drives   Overview Module port connections and interfaces can...
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Interprocess synchronization and communication

Interprocess synchronization and communication

Interprocess synchronization and communication We will discuss the following: — Semaphores — Mailboxes — Named events   Overview High-level and easy-to-use synchronization and communication mechanisms are essential to control thekinds of interactions that occur between...
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Event Scheduling Semantics in SystemVerilog

Event Scheduling Semantics in SystemVerilog       Scheduling semantics Event-based simulation scheduling semantics SystemVerilog’s stratified event scheduling algorithm Determinism and nondeterminism of event ordering Possible sources of race conditions PLI...
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Processes in SystemVerilog

Processes in SystemVerilog

  Processes in SystemVerilog We will discuss on following Structured procedures (initial procedures, always procedures, final procedures) Block statements (begin-end sequential blocks, fork-join parallel blocks) Timing control (delays, events, waits, intra-assignment) Process...
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