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VERILOG, ADVANCED DIGITAL & ANALOG DESIGN TRAINING

(Classroom & Online live Training)

Course Schedule & Fee:

  • Course: VLSIGuru Institute 6 weeks summer internship & training in VLSI
  • Duration : 6 Weeks | Schedule : 4 sessions per week & 3 hours per session
  • Fee : INR 7,000/- (including service tax)
  • Course start date : 10/June | Course End Date: 21/July
  • Demo Session: 10/June, 5:00PM to 7:00PM (Both classroom and online training at same time)
  • Trainer:
    • Dual Degree (Btech & MTech) in VLSI, IIT Madras, 12+ years exp.
    • Currently working as a senior director in a design services company.
  • Registration : Mail: contact@vlsiguru.com
  • Students attending in the class will register at institute
  • Students attending online: Initiate Fee transfer after attending demo session on 10/June
    • Online training offered using gotomeeting

Course Contents:

  • Verilog for Design and Verification

       Verilog Language Constructs

  • Introduction to Verilog HDL |  Module   | Data Types | Verilog Operators
  • Dataflow Modeling | Behavioral Modeling | Gate Level Modeling
  • Structural Modeling | Operators | Assignment Statements | procedural statements | always | initial | delay modeling | compiler directives | System Tasks & functions | Compiler Directives |File Input & Output | State Machines | Verilog Registers | Table | Primitives | Generate | Systems tasks & functions | Synthesis | PLI & VPI | | Design implementation using RTL | Testbench coding

     Design & Verification Projects covered (Tool used: Mentor graphics Questasim)

  • Flipflop & registers | Various Counters | PISO | POSI | Standard combinational circuits | Dual Port RAM | Pattern Detector |Vending Machine | Traffic Light controller | CRC generation
  • Watchdog timer | Synchronous FIFO | Asynchronous FIFO | Interrupt Controller | SPI Controller | I2C Controller | UART Controller

Advanced Digital Design

  • Numbering system | Karnaugh maps | Timing diagrams | Pipelining | Flipflop
  • Latch | Various types of FF’s, Latch’s | Various Counters (applications) | FIFO
  • Data transfer synchronization between components | Race condition
  • Meta stability | Multiplexer, Using MUX to create various gates, FF | Decoder, encoder, priority decoder | Parity generation | Half adder, full adder | Truth table for HA, FA, Mux, counters | Buffer, inverter | PLL, VCO, clock generation
  • Clock multiplication | Clock division | clock domain crossing | Reset | Power management in SOC | State machines | Register
  • Memories | Synthesis | Predict design output | Gate level simulations
  • Debugging incorrect designs | Clock distribution | Active low and active high
  • PISO, SIPO | Comparator | Designing circuits for various requirements
  • CRC calculation logic | Pattern detector FSM

Analog Design Training

  • Basics & Introduction to domains of analysis(Time, Frequency, S-domain)
  • MOSFETS I-V characteristics and operating point analysis | MOS Device Operation | RC Circuits | Threshold Voltage (Body Effect)
  • Device Ron | MOS Device as Current Source & Sink | MOS Current Mirrors | Differential Amplifier & Two Stage Differential Amplifiers | Voltage & Current Reference Generators (BG) | Voltage Regulators Design Basic
  • CMOS process technology | CMOS Based circuits
  • Simple CMOS amplifier topologies | MOSFET in deep submicron technology
  • Differential Amplifiers | Feedback | Understanding SPICE simulations(AC, DC, Transient, Noise)

VLSI Summer Training Overview Video:

FAQs:

  • Why Fresher should do this course?
    • Course will help bridge the industry – academia gap, helps student gain knowledge as for industry expectations. In general what is covered as part of graduate course curriculum is not sufficient.
    • Every VLSI Design is driven by a set of common digital and analog design concepts, this course helps student gain good understanding on above concepts, hence making it easier to ramp up on any complex design.
    • Course will give student with exposure to standard designs like FIFO, State machines, controllers, etc. This will help student choose right Btech/MTech project, which will add lot of value addition to student’s resume.
    • Majority of VLSI fresher interviews focus on digital design concepts, Verilog and basics of Analog circuits. This course will make student proficient with all these concepts.

 

  • Target audience?
    • 4th and 6th semester BTech/BE students seeking summer internship
    • 2nd semester MTech/ME students seeing full time internship
    • Any graduate passionate about VLSI and does not know where to start.

 

  • What if few sessions missed?
    • Missed sessions are covered by backup sessions.

 

For Further Details:

  • Mail: contact@vlsiguru.com | Phone & Whatsapp: 9986194191
  • Address: #25, 1D Main road, Vijaya Bank Colony Extn, Horamavu, Bangalore – 43
Online VLSI Training