There are two kinds of internships.
- One, You join a company where they will give you a junk work which their permanent staff don’t want to do. They will pay you some stipend for doing the same. It doesn’t offer any significant learning.
- Second, you join internship where you learn new languages, protocols and skillset which you don’t learn as part of college curriculum.
We offer internship in 2nd category, where student gets to learn new skill set, which improves the candidate employability for current job requirements.
We provide option to the student to choose the internship domain/course based on their current expertise, rather than offer one common course for every intern.
Student based on prior expertise with Verilog, can choose one the the below three courses for the 6 weeks internship. It is highly recommended for everyone pursuing 3rd or 4th year of BE/BTech.
These courses are very helpful for those attending product company internship interviews. Our interns have 100% success rate in product company internship placements.
Students expecting internship to be offered in 2K per month is unrealistic. Consider a training institute offering 6 months course, how much do they charge for the course? Divide it by 6 to get per month fee charged. Now compare with internship fee. This is how, we arrived at 6K fee for summer internship. We do consider group discounts.
Student can choose one of the below four domains for the summer internship.
- Verilog
- How Verilog differs from other programming languages?
- Verilog language concepts
- registers, nets
- Vectors, Array
- Memories
- Data types
- Operators
- Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
- Procedural Blocks
- Continuous assignments
- Procedural Statements
- Generate
- State Machines
- Gate Level Implementation
- Hierarchical modeling
- Verilog Programming Interface(& PLI)
- Pipelining
- FSM : Mealy and Moore
- FSM State encoding styles
- Flipflop (Synchronous & Asynch Reset), Latch
- Counter-Gray code counter, modulo, ring, johnson, up counter, down counter
- Shift register implementation
- Half adder, full adder, multiplexer
- Dual port memory write, read design & testbench
- encoder, decoder, various gates
- Primitive implementation using table, endtable
- Pattern detector
- Traffic light controller(TLC)
- CRC generation code
- Watchdog timer implementation
- Synchronous FIFO
- Asynchronous FIFO
- Memory implementation
- example to showcase race condition using blocking assignments
- system task usage: $display, $monitor, $strobe
- PLI, VPI implementation
- Clock generation with Duty cycle & Jitter
- Interrupt Controller
- SPI Controller
- I2C Controller
- UART Controller
- VLSI design flow
- Semiconductor device fundamentals
- IC fabrication
- Linux commands
- PD project with basic PnR flow exposure
- Number systems
- Radix conversions
- K-maps, min-terms, max terms
- Logic gates
- Realization of logic gates using mux’s and universal gates
- Compliments (1/2/9/10’s complement)
- Arithmetic operations using compliments
- Boolean expression minimization, Dmorgan theorems
- POS and SOP
- Conversion and realization
- Adders
- Half adder
- Full adder
- Subtractor
- Half subtractor
- Full subtractor
- Multiplexers
- Realizing bigger Mux’s using smaller Mux’s
- Implementing Adders and subtractors using Multiplexers
- Decoders and Encoders
- Implementing Decoders and Encoders using Mux and Demux
- Bigger Decoder/Encoder using smaller Decoder/Encoder
- Comparators
- Implementing multi bit Comparators using 1-bit Comparator
- Latch, Flipflop
- Latch, Flipflop using Gates or Mux’s
- Different types of FFs
- FF Truth table
- Excitation tables
- Realization of FF’s using other FF’s
- Applications of FF’s, Latches
- Counters
- Shift registers
- Synchronizers for clock domain crossing
- FSM’s
- Mealy, Moore FSM
- Different encoding styles
- Frequency dividers
- Frequency multiplication
- STA
- Setup time, Hold time, timing closure
- fixing setup time and hold time violations
- Launch flop, capture flop
- Radix and number systems
- Complements
- Logic gates and realization
- Multiplexor based questions
- Decoder based questions
- Boolean expression minimization
- Combinational circuits
- Latches and flipflops
- Counter design and applications
- Frequency division and multiplication
- Edge detectors
- Shift registers
- FSM based questions
- Code conversion
- Predict output of given circuit
- Develop a circuit for given requirements
Course Overview
VLSI summer internship is a 6 weeks program enabled for providing participants with expertise on VLSI Verilog or Physical design practical aspects.
It is highly recommended for student pursuing 3rd year of BTech/BE.
| Course | VLSI summer internship |
|---|---|
| Duration | 6 weeks |
| Next Batch | Available through out the year |
| Mode of training | Classroom training & Live online training Course can also be done in hybrid mode. |
| Batch Size | 20 |
- Course presentations for all topics
- Session notes
- Lab documents with detailed steps
- User guides
- Each aspect of course is supported by lot of practical examples
- Dedicated full day lab sessions to ensure student does complete testbench development from scratch
- Yes, You will have option to view the recorded videos of course for the sessions missed
- You will have option to repeat the course any time in next 1 year
- Yes, Course fee also includes support for doubt clarification sessions even after course completion
- You have option to mail you queries
- Option to meet in person to clarify doubts
Experienced Trainer
- 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
- Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
- Experience of working on multiple complex module level projects
- 1-1 Dedicated mentor support
- Mock interview
- Industry standard projects
- Support with resume update