VLSI Functional verification
1-1 training Highlights
- 165 hours of 1-1 training at student flexible timings
- Access to all the session recorded videos
- Complete guided project support with 24x7 server and tool access
- Course content can be customized(topics added and removed)
- Trainer support outside teaching hours for doubt clarification
- Regular mock interviews and assessments for performance tracking
- References in product companies for job support
- Support with office work debug (for working professionals)
Course content - Hourly breakup
| Topic | Duration(Hours) |
|---|---|
| Number systems, radix conversions | 1 |
| K-maps, min terms, max terms, POS and SOP | 1 |
| Logic gates, realization of logic gates using mux and universal gates | 1 |
| Compliments (1/2/9/10’s complement), Arithmetic operations using compliments | 1 |
| Boolean expression minimization, D-morgan theorems | 1 |
| Adders – Half adder, Full adder, Subtractors Half subtractor, Full subtractor | 1 |
| Adders and subtractors using Mux’s | 1 |
| Multiplexers – Realizing bigger Mux’s using smaller Mux’s | 1 |
| Decoders and Encoders, Decoders and Encoders using Mux and Demux | 1 |
| Bigger Decoder/Encoder using smaller Decoder/Encoder | 1 |
| Comparators, multi bit comparators using 1 bit comparator | 1 |
| Latch, Flipflop – realization using Gates or Mux’s | 1 |
| Different types of FFs – Excitation tables | 1 |
| Applications of FF’s, Latches – Counters, Shift registers | 1 |
| Synchronizers for clock domain crossing | 1 |
| FSM – Mealy, Moore FSM | 1 |
| FSM – Mealy, Moore FSM implementation using different types of FFs | 1 |
| Frequency dividers, Frequency multiplication | 1 |
| Total | 18 |
| Topic | Duration(Hours) |
|---|---|
| Verilog constructs | 2 |
| Combinational logic implementation | 5 |
| Sequential logic implementation | 3 |
| Advanced Verilog language constructs | 10 |
| Verilog projects | |
| Memory verilog coding and TB development | 3 |
| Synchronous and Asynchronous FIFO design and verification | 4 |
| SPI Controller | 4 |
| Pattern detector | 2 |
| CRC generation | 2 |
| Total | 35 |
| Topic | Duration(Hours) |
|---|---|
| Data types, operators, arrays | 6 |
| Object oriented programming | 12 |
| Interface, program, Inter process synchronization | 3 |
| Constraints and randomization | 4 |
| Functional and code coverage | 4 |
| Assertions | 3 |
| Other SV language constructs | 3 |
| SV Test bench setup for memory | 5 |
| Total | 40 |
| Topic | Duration(Hours) |
|---|---|
| UVM base classes, UVM TB hierarchy | 3 |
| Root, objections, phases, Command line processor | 3 |
| Reporting classes | 2 |
| UVM config DB and Resource DB, Factory | 3 |
| TLM1.0 | 2 |
| Sequences, sequence library | 2 |
| RAL, register model coding | 3 |
| UVM Test bench setup for memory | 4 |
| Total | 22 |
| Topic | Duration(Hours) |
|---|---|
| SPI Protocol | 0 (already covered in Verilog) |
| I2C Protocol | 2 |
| APB protocol | 1 |
| AHB protocol | 4 |
| AXI protocol | 5 |
| Total | 12 |
| Topic | Duration(Hours) |
|---|---|
| AXI VIP development using SV & UVM | 6 |
| Ethernet MAC functional verification using SV & UVM | 24 |
| Total | 30 |
| Topic | Duration(Hours) |
|---|---|
| Linux basic commands – File and directory handling | 1 |
| Linux advanced commands – sed, awk, grep, xargs | 2 |
| Python variables, Lists, tuples, dictionaries | 1 |
| Operators, loops, working with files | 2 |
| Regular expressions, Python hands on examples | 2 |
| Total | 8 |