VLSI Online Training in Functional Verification


VLSI Online Training in Functional Verification (VG-VTO) course is structured to enable engineers develop their skills in full breadth of SystemVerilog, UVM & OVM features in complex testbench development. VG-VTO course is targeted towards both BE, ME freshers and verification engineers who are used to Verilog based functional verification and would like to explore SystemVerilog, UVM & OVM based verification. Course has been framed in a way to make functional verification learning a fun and interesting activity. Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple industry standard projects, all of these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VG-VTO.

  • AXI Protocol & AXI VIP Development
  • Memory Controller Functional Verification
  • UVM & OVM Base class and Macro usage with detailed examples on each construct usage
  • AHB Protocol, AHB UVC development & AHB I/C functional verification
  • Register layer development for USB2.0
  • USB2.0 Core Functional verification


  • Online Training is offered for all course including SV, UVM, OVM, Verilog, SoC, PERL, etc
  • Online Training syllabus & duration is same as of corresponding classroom course offered
  • Please refer to class room training course page for specific course syllabus


Course Online VLSI frontend course for experienced engineers
Duration 21 weeks
Next Batch 22/Novmber
Demo Session 22/Nov (9AM to 1PM)
Course Enrol 23/Nov
Schedule Saturday & Sunday(8:30AM – 4:00PM India time)
8:30AM – 12PM (Trainer led theory and lab sessions)
1PM to 4PM (Mentor guided lab & assignment solving sessions)
New batch starts every 8 weeks
Fee INR 34000 +GST at 18%
Tool Questasim & VCS
Mode of training Classroom training at VLSIGuru Institute, Banaswadi, Outer Ring Road
Online training using live training sessions
Tool Access Tool access for 1 year duration at institute premises.
Certificate Issued based on 50% assignment completion as criteria
Admission criteria Student need to undergo evaluation test based on Verilog Digital Design and Aptitude
Assignments 40
Trainer 12+ Years exp in RTL design & Functional verification


What are the Course Prerequisites?

  • Expertise on Verilog Language
  • Exposure to Testbench component coding using Verilog

Does course cover practical sessions on UVM usage?

  • Each aspect of course is supported by lot of practical examples
  • Ethernet loopback design used as reference design towards implementing and learning different SV aspects
  • AHB Interconnect is reference design from Session#1 towards implementing and learning different UVM aspects
  • All UVM course examples, AHB UVC, AHB Interconnect and USB2.0 Core Verification environment implemented from scratch as part of sessions
  • Dedicated full day lab sessions to ensure student does complete testbench development from scratch

Is it possible to cover so many things in 9 weeks?

  • We have done it for 23 Batches so far, next batch is no exception
  • Course requires student to spend at least 6+ hours of time a week to revise the concepts

What if I miss few sessions during course?

Each session of course is recorded, missed session videos will be shared

Course has started few weeks back, can I still join the course in between?

  • Yes, You will have option to view the recorded videos of course for the sessions missed
  • You will have option to repeat the course any time in next 1 year

Do you offer support after course completion?

  • Yes, Course fee also includes support for doubt clarification sessions even after course completion
  • You have option to mail you queries
  • Option to meet in person to clarify doubts

Course Material

Course Material Shared:

  • SV quick notes, IEEE manual
  • SV Checklist
  • SV Lab Examples
  • AXI VIP Code
  • Ethernet loopback design Testbench Code
  • Memory controller Testbench Code
  • UVM User Guide
  • UVM Checklist
  • UVM Lab Examples
  • AHB UVC Code
  • AHB Interconnect Testbench Code
  • SPI Register Layer code
  • USB2.0 Core testbench Code


Target Audience:

  • Verification engineers looking to learn advanced verification techniques
  • MTech & BTech freshers who are well versed with Verilog, and would like to learn advanced verification
  • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
  • Engineering college faculty looking to enhance their VLSI skill set


Trainer Profile

  • 14+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
  • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
  • Experience of working on multiple complex module level projects
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