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VLSI Backend Training

  • DFT - design for testability consists of IC design techniques that add testability features to a hardware product design. The added features make it easier to develop and apply manufacturing tests to the designed hardware. The purpose of manufacturing tests is to validate that the product hardware contains no manufacturing defects that could adversely affect the product’s correct functioning.

    Tests are applied at several steps in the hardware manufacturing flow and, for certain products, may also be used for hardware maintenance in the customer’s environment. The tests are generally driven by test programs that execute using automatic test equipment (ATE) or, in the case of system maintenance, inside the assembled system itself. In addition to finding and indicating the presence of defects (i.e., the test fails), tests may be able to log diagnostic information about the nature of the encountered test fails. The diagnostic information can be used to locate the source of the failure.

    In other words, the response of vectors (patterns) from a good circuit is compared with the response of vectors (using the same patterns) from a DUT (device under test). If the response is the same or matches, the circuit is good. Otherwise, the circuit is not manufactured as it was intended.

    DFT plays an important role in the development of test programs and as an interface for test application and diagnostics. Automatic test pattern generation, or ATPG, is much easier if appropriate DFT rules and suggestions have been implemented.
    • Design For Testability

      • DFT Basics
      • SoC Scan architecture overview
      • Types of Scan
      • ATPG DRC Debug
      • ATPG Simulation Mismatch Debug
      • DFT Diagnosis
      • JTAG
      • MemoryBIST
      • LogicBIST
      • Scan and ATPG
      • Test compression technigues
      • Hierarchical Scan Design
    • Next Batch: 3/Sep, 2:00PM - 6:00PM
    • Duration: 8 Weeks
    • Fee : INR 12,000
    • Tools : Tessent FastScan(Mentor Graphics)
    • Access to tool using remote connection
    • Certificate of course completion
    • Options to repeat the course

    Registration:
    • Attend Demo Session on 3/Sep, 2:00PM-6:00PM
    • Registration on 4/Sep
    • What are the Course Prerequisites?

      • Expertise on Verilog
      • Exposure to Testbench component coding using Verilog
    • Does course cover practical sessions on SystemVerilog usage?

      • Each aspect of course is supported by lot of practical examples
      • Ethernet loopback design used as reference design from Session#1 towards implementing and learning SystemVerilog constructs
      • All SystemVerilog course examples, AXI VIP, and Memory Controller Verification environment implemented from scratch as part of sessions
      • Dedicated full day lab sessions to ensure student does complete testbench development from scratch
    • Is it possible to cover so many things in 8 weeks?

      • We have done it for 23 Batches so far, next batch is no exception
      • Course requires student to spend at least 6+ hours of time a week to revise the concepts
    • What if I miss few sessions during course?

      • Each session of course is recorded, missed session videos will be shared
    • Course has started few weeks back, can I still join the course in between?

      • Yes, You will have option to view the recorded videos of course for the sessions missed
      • You will have option to repeat the course any time in next 1 year
    • Do you offer support after course completion?

      • Yes, Course fee also includes support for doubt clarification sessions even after course completion
      • You have option to mail you queries
      • Option to meet in person to clarify doubts
  • Course Material Shared:
    • DFT quick reference manual
    • DFT Checklist
    • DFT Tool user guide
  • Target Audience:
    • Verification engineers looking to learn advanced verification techniques
    • MTech & BTech freshers who are well versed with Verilog, and would like to learn advanced verification
    • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
    • Engineering college faculty looking to enhance their VLSI skill set
  • Trainer Profile
    • 10+ years of rich experience of working in DFT domain across various mobile, networking, high speed peripheral domains.
    • Experience of working on multiple complex module level projects
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