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Verilog for Design & Verification

  • Verilog for Design & Verification (VG-VERILOG) course is structured to enable engineers develop their skills in full breadth of Verilog Constructs in Complex Design implementation and Directed testbench Setup. VT-VERILOG course is targeted for both design & verification engineers who want to gain expertise in using Verilog for design & testbench development.
    Course will also focus on Advanced Digital design concepts & Basic Analog design concepts. VG-Verilog course is a 5 week course to ensure that student is completely prepared with all Verilog, Digital & Analog design concepts, before he start looking out for job.

    Course has been framed in a way to make Verilog learning a fun and interesting activity. Every aspect of course is supported with multiple examples to enable easier & quicker understanding. Course also covers multiple design implementation examples and testbench setup for same, all of these executed from scratch. Lab sessions are planned at regular intervals to enable student work on these projects from scratch with trainer guidance. Below is quick overview of what is covered as part of VT-VERILOG

    • Verilog language constructs with detailed examples on each construct usage
    • Multiple Design Coding & Testbench development
    • Access to Questasim tool
    • Hands on labs & Hands on projects
    • Basic Digital Design Concepts
    • Advanced Digital Design Concepts
    • Basic Analog Design Concepts
    • Introduction to Verilog

      • Introduction to Verilog Course
      • Module
      • Data types
      • Vectors, Arrays
      • Operators
      • Various styles of Modeling: Data Flow, Behavioral, Gate level, Switch level
      • Procedural Blocks
      • Continuous assignments
      • Procedural Statements
      • Generate
      • State Machines
      • Gate Level Implementation
      • Verilog Programing Interface(& PLI)
    • Commonly asked Verilog Design Examples : All covered in course training

      • Flipflop (Synchronous & Asynch Reset), Latch
      • Counter-Gray code counter, modulo, ring, johnson, up counter, down counter
      • Shift register implementation
      • Half adder, full adder, multiplexer
      • Dual port memory write, read design & testbench
      • encoder, decoder, various gates
      • Primitive implementation using table, endtable
      • Pattern detector
      • Coin counter for tea vending machine
      • Traffic light controller(TLC)
      • CRC generation code
      • Watchdog timer implementation
      • Synchronous FIFO
      • Asynchronous FIFO
      • Memory implementation
      • example to showcase race condition using blocking assignments
      • system task usage: $display, $monitor, $strobe
      • PLI, VPI implementation
      • Memory controller RTL understanding, architecture understanding
      • Clock generation with Duty cycle & Jitter
      • PCIe different layer implementation
      • Interrupt Controller
    • Verilog for Verification

      • Verification of all above designs using Verilog
  • Course Verilog for Design & Functional Verification
    Duration 5 weeks
    Next Batch 02-Sept
    Demo Session 02-Sept (5:00PM - 7:30PM)
    Registration 03-Sept
    Schedule Both Saturday & Sunday(5:00PM - 7:30PM India time) Wednesday(6:00PM - 8:00PM)
    New batch starts every 6 weeks
    Fee INR 5000/- + Tax
    Tool Questasim
    Mode of training Classroom training at VLSIGuru Institute(Horamavu)
    Online training using live training sessions
    Tool Access 24X7 access using VPN
    Certificate Issued based on 50% assignment completion as criteria
    Batch Size 20
    Assignments 24
    Placement support Interview opportunity in at least 6 companies
    100% job on completion of all assignments
    and scoring good grade in monthly evaluation test
    Trainer 12+ Years exp in RTL design & Functional verification
    • What are the Course Prerequisites?

      • No per-requisites. Good to know C language & exposure to Digital Design concepts
    • Does course cover practical sessions on UVM usage?

      • Each aspect of course is supported by lot of practical examples
      • Dedicated full day lab sessions to ensure student does complete testbench development from scratch
    • Course has started few weeks back, can I still join the course in between?

      • Yes, You will have option to view the recorded videos of course for the sessions missed
      • You will have option to repeat the course any time in next 1 year
    • Do you offer support after course completion?

      • Yes, Course fee also includes support for doubt clarification sessions even after course completion
      • You have option to mail you queries
      • Option to meet in person to clarify doubts
  • Verilog Material Access
    Course material Shared over google drive consists of IEEE Manual-Labs & project code
    Course page access Get login details from Admin
    Assignments-Checklist-Session notes Course page
    Labs Shared as part of course material and also shared every week
    Gvim install & usage Youtube video shared as part of course guidelines
    How to use course material Share as part of Course material
    Resume update Share as part of Course material
    Session Notes Uploaded to the course page
    Interview Questions Uploaded to course page
    Labs for every week session sent as mail attachment at the end of every week
  • Target Audience:
    • MTech & BTech freshers would like to start learning directed verification
    • Engineers with prior experience in other domains of VLSI or experience non-VLSI domains, want to make career in Functional Verification
    • Engineering college faculty looking to enhance their VLSI skill set
  • Trainer Profile
    • 10+ years of rich experience of working in Functional Verification domain across various mobile, networking, high speed peripheral domains.
    • Experience of working on functional verification of Multiple Complex SOCs, multiple Sub systems
    • Experience of working on multiple complex module level projects
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