SESSION#1

1. two asepcts
   o Verilog langauge training => 5 weeks => assessment test
   o Verilog hands on project training => 3 weeks

2Q. is linux not for Design verificaiton training?

3. 4 months
   Verilog, SV, UVM
4. DFT
   Input: RTL code or Gate level code
   Output:
   1. Test vectors
      test_vector1: 10101010101111000101010101010101101010100101010
      test_vector2: 000010110101010101111101010101010010101010101010001
   2. Gate leve code or RTL code updated for self testing logic
      o which will help detect any manufacturing defects in the design.
5. Functional verification
   o main role: catch bugs in the design
6. is rtl designing and design verification is same?
   • different
7. what about the projects for DFT?which tool is using
   o IRIS
   o Understand whole DFT flow

8Q. if possible, can yobugsu show us how this error is being detected now, using testbench and tool?

9Q. what are the other scope for DESIGN Varification Engineer .
o to catch the design bugs

10Q. It means DFT before manufacturing & Design Verification engg after manufacturing…
o both happens before manugaturing

11Q. is tools or softwares are same in company which we are using in labs?
o yes

12Q. RTL design is verifying or working on code and dft means working on TB sir?
o No
o DFT doesn’t involve any TB at all(except for when you run simulation)

13Q. should we be preparing for verilog seperately or sessions are enough sir.
o Verilog 4-5 sessions are enough

14Q. every domain has its importance but to compare btw DV & DFT which is better and wil have good growth

15Q. There is an UVM course for 8 weeks on the website. Should we take up that course if we get into UVM? Since this course also includes UVM in syllabus, is it sufficient?
o UVM = UVM Essentials + UVM Advanced

16. text editors
    GVIM
    notepad++
    kedit
    emacs
17. what is Verilog?
    o Hardware description langauge
    Why Verilog is required?
    why modelsim is required?
18. 3 bit up counter (time taken in digital session: 30 minutes)
    0 -> 1 -> 2…7->0..
    truth table
    k-maps
    boolean expression
    draw the circuit
    implement the circuit
19. 20 bit up counter (time taken in digital session: 30 minutes)
    0 -> 1 -> 2…7->0..
    truth table
    k-maps
    boolean expression
    draw the circuit
    implement the circuit

truth table entries: 2**10 = 1024 rows
kmaps = 1024 boxes in kmap
it may take 1 full day to do this.

20Q. What is verilog AMS?
AMS: Analog mixed signal

Verilog : Digital design
Analog compoennts coding needs Verilog AMS langauge

21. Basic coding examples of Verilog
    o combinational => initial 1 week on this
    o Multiplexor, decoder, encoder
    o full adder, half adder
    o realizing gates usng other gates
    o subtractor
    o priority encoder
    o comparator
    o ALU
    o sequential => 4 weeks on this
22. half adder
23. Verilog supports 4 styles of coding the designs
    o data
    o gate level
    o behavioral
    o it is very close to English.
    o switch level (redundant)

SESSION#2

1. need for a new langauge?
   o concept of time => nature of sequential circuits
   o concept of structure
   o concept of concurrent running processes
   o typing on KBD
   o online session
   o presentation is displayed to Projector
2. Why we can’t use Hindi for Hardware description?
   o there are no compiler for Hindi
   o there are no synthesis tool for Hindi
   o Hindi has 5000 words
   o Verilog has only 100 words
3. Mux
   behavioral => always
   data flow => assign
   gate level => gates
4. initial begin
   a = 10; //giving value of 10
   //a is registering value of 10 20; //20 units(20ns) of delay a = 40; //giving value of 40
   end
5. why we are store value in register?
6. i0 = $random; //$rnadom : generates a random number
   $ : Langauge provided task/function
   random: generating a randon number
   $random: generates a 32 bit random number

include “stdio.h” => printf, scanf

7Q. why input as reg and output as wire ??

• Basic guideline:
  o any variable on the LHS of a statement inside always or initial block, must be ‘reg’
  o everything else must be ‘wire’
  o given a variable, if not declared anything, it is wire by default

1. wire, reg
   wire => electrical wire
   o till the time electricity supply is there, they will have the value.
   reg => battery based bulbs
2. vlib work => library creation
   vmap work work => library mapping
3. I think notepad++ is easy to use other than GVIM

11Q. When we create a new folder for different project. Is it required to define vlib…
o modelsim => yes
o questasim => no

12Q. in the design module we are making the output as reg and input as wire …..why output is reg(why we are storing it)

13Q. why we need these i.e vlib and vmap …please explain
library: the way things are stored inside the tool

14Q. can we write design and TB in same .v file ?
– yes

15Q. in tb you are using `include statement is it mandatory?
o not mandatory

16Q. do we need to necessarily to take as “work”…or some other name
o not compolsory
o we can use some other librayr name also

17Q. $random genereates randon number, then how will know it is 0 or 1 it will be different apart from this. then how will work 2×1 mux?

18. {i0, i1, sel} = $random; //$rnadom : generates a random number
    $random generates 32’b1010_1010_1100_1010_0010_1010_1110_1110

19Q.
why $monitor not at the bottom of first initial statement after repeat statement

20.
y = i0~sel | i1.sel
and, not, or, and

SESSION#3

materials

1. inskill.in
2. added to some group
   o whatsapp group
   o skype group
3. access to recorded videos from live sessions
4. access to all the ppts, assignments
5. installed Modelsim tool and know how to use the tool
6. Individaul GOogle drive link
   o Sreenivas
   o Digital
   o Verilog
   o ASGN1 => submit your solutions in to that folder
   o ASGN2 => submit your solutions in to that folder

revision:

1. HA, FA using HA
2. 2×1 mux, 4×1 mux using various abstraction levels

questions:

1. theoretical
   o what is difference between vector and array
   reg [7:0] a; //Vector : all 8 bits stored in same address location
   reg b [7:0]; //Array : 8 bits stored in 8 different locations, one bit in each location
   analogy:
   vector: 8 family member in same house
   a = 8’b1011_0011
   a[0] = 1;
   a[1] = 1; //also posisble
   array: 1 member of each house, 8 continuous houses
   o post man comes, he want to give 8 post to each perion
   b = 8’b1011_0011; //not possibel in case of array
   o b rpresents 8 different address locations
   b[0] = 1; //possible
   b[1] = 1;
   b[2] = 0; so on
   reg [0:7] c;
   o reg [2:0] b [7:0]; //Array of 8 locations, each having 3 bits
   o 8 houses, each house having 3 people
2. assignemtn specific
   o 8 bit HA
   o there won’t be any carry in
   o case and casex
   o why casex is used in priority encoder? why case doens’t work?
   case requires more lines of code. o if a=1 and b=0, both are one bit inputs and c is a 2 bit number the what is the instruction to concatenate a and b to c lik
   c = {a, b} //if we want a in MSB
   o why we use $random, how it works, and syntax
   o encoder using mux
   o how to implement code using case
   2×1 mux using case
   always @(*) begin
   case (sel)
   1’b0 : y = i0;
   1’b1 : y = i1;
   endcase
   end o where to use reg and where not to use
   – always or initial block, variables on LHS => declare them reg o while using case statement in 4x1mux,i had given default:y=1’bx, but in simulation it gives wrong answer sometime y
   o debug support session o please explain 4×1 using 2x1mux
   o Difference between using ifelse & case statements in behavioral design?
   o Can we declare different size vectors as same input? Like, input [3:0]a, [1:0]b;
   No
   o Can we use more than one module in same.v file?
   yes
   o does interchanging of input & output ports matter while defining itself sir?
   o no
   o How many times we can use $ monitor in a code
   o any number of times o always,initial,,begin,end
   o
   o what is differnce b/w variable nd reg??
   o Verilog don’t have anything called as variable o explain priority encoder
   o casex o 8×1 using only 4×1 using vector. [7:0]
   o o Question: When we use “inout” port? – PLease give example.
   o explain procedural block,nonprocedural block
   o what shouid be the default output combination for a encoder for both normal encoder and priority encoder
   o when delay is not used in repeat, will loop only once ? or will it complete all runs and then take the final value ?
   o in mux8x1 i had written code for 8x1mux using 2×1 mux but it gives correct ans for only one bit, i had tried for more than one bit it doesnot give correct ans..
   o in coding point of view how to code these things (basic gates design using mux) & there is one more qst in assgn1 (encoder&decoder using mux)
   o please explain some basic commands in theory of verilog programming
   o how to give $random in a vector
   o 8×1 using only 4×1 using vector. [7:0]
   o difference between display and monitor
   o in the design of encoder or mux which order we should follow while declaring inputs.. whether LSB should be first or MSB should be first?
   o explain blocing and nonblocking
   o data type in verilog
   o difference between initial ad always
   o Use of $random
   o explain concatenation style of implementation.
   o explain assign statement
   o various operators…
   o how to give a random input in vector
   o while declaring inputs for 8:1 mux should we prefer declaring individually or we go for vector?
   o Parameterizable full adder
   o Design encoder using gate?
   o explain significance of dataflow behavioral and gate level modelling, which one to use when?
   o which style of coding should we focus on.
   o why do we cant assign a value of wire to the output port?
   o explain diffrence between symbol & and && with example
   o gate level codeing
   o how to use circle before any statement?
   o How to write the “`include “for gate level , behavioral and structural
   o why $random gives only 0,1 why not choose other value
   o how reg, wire varies in 3 styles of modelings
   o 4-bit counter how to write logic
   o how can i judge which model is better for particular program? either data or behavioral or any other
   o explain instansiation of module
   o can we use assign for reg variable
   o What is the most efficient way of mapping?
   o difference between + and | operator
   o how we use assign astatement in sequential circuit o please explain everyting in sequence manner for verilog program so that we can solve every question from assignment…
   o will there not be theory session where you will explain everything in sequence?or do we have ask ques like this??
3. when we use parameter in design, is it compolsory to use parameter in TB also?
   Yes.

3.
case, if, for, while, forever, repeat
o all these statemnts must be written only inside always or initial block.,

4
16 => Hexa, Binary, Oct or decimal?

5. every programming langauge has if and case
   o in lanauges, case is implemented as ‘switch’
6. always @(*) Only for combinational logic

7Q. where do we use single input and where do we use vector input?
o as much as posisble we always use ‘vector’

8Q. idfference betweeen
reg [3:0] i = 4’b1000;
reg[3] = 1
reg [0:3] i = 4’b1000;
reg[3] = 0
reg[0] = 1

9. temparate details of Bangalore for 1 month
   real tempArray[29:0];
   real [29:0] tempvector; ==> not possible

10Q.
input [4:0]a;
input [4:0]b;

input [4:0] a, b; //both a, b are 5 bit variables
input a, [4:0] b; //this is not possible

11Q.
input [7:3] a; //possible
input [-7:-3] a; //possible
input [7:-3] a; //possible

12. data_type array_name[index];
    integer intA[7:0];
    reg regArray[3:0];
13. input a; //1 bit variable

14Q. Q Vector is also possible that define the temp of one one location ???
reg [31:0] temp;
temp is a integer, it needs 32 bit store

15Q. data types only for arrays? N not for vectors…
for vector, data type is compolsiry 1 bit variable only
reg or wire.

integer [3:0] a; //not possible
reg [3:0] a; //possible
wire [3:0] a; //possible

16. case and casex
    priority encoder
    casex(in) //4’b1100, 4’b1001
    4’b1xxx : out = 2’b11;
    4’b01xx : out = 2’b10;
    4’b001x : out = 2’b01;
    4’b0001 : out = 2’b00;
    endcase
    o casex => case branch ordering is important
    o casex treats both x and z as don’t care is it possibel to do with case?
    o it is possible
    case(in) //4’b1100, 4’b1001
    4’b1000 : out = 2’b11;
    4’b1001 : out = 2’b11;
    4’b1010 : out = 2’b11;
    4’b1011 : out = 2’b11;
    4’b1100 : out = 2’b11;
    4’b1101 : out = 2’b11;
    4’b1110 : out = 2’b11;
    4’b1111 : out = 2’b11; 4'b0100 : out = 2'b10; 4'b0101 : out = 2'b10; 4'b0110 : out = 2'b10; 4'b0111 : out = 2'b10; 4'b0010 : out = 2'b01; 4'b0011 : out = 2'b01; 4'b0001 : out = 2'b00; endcase
17. why we use $random, how it works, and syntax
    o to gneerate a random integer
    o integer is 32 bit size
    32’b…… (32 bits) o {i0, i1, i2, i3, sel} = $random; //$rnadom : generates a random number
    $rnaomd = 32’b1010_1100_1111_1100_0000_0101_0001_1101
    sel =
18. use concatenation operator to swap two bytes
    reg [15:0] a, b;
    //we want to swap bytes of a and b
    b = {a[7:0], a[15:8]};
    a = 16’b1234;
    b = 16’b3412;
19. 2×1 encoder using 2×1 mux
    o 2 bit encoder
    i1 i0 y
    0 0 x
    0 1 0
    1 0 1
    1 1 x
20. 2×1 encoder using 4×1 mux
21. 4×2 encoder using 4×1 mux
22. initial is used in TB, always is used in design
23. is strucural code same as gate level coding.
    • gate level coding is one sub aspect of strucural coding

25.
cd ../../.. => go 3 folders up

26
integer a;
reg [31:0] a;