SESSION#1

  1. two asepcts
    o Verilog langauge training => 5 weeks => assessment test
    o Verilog hands on project training => 3 weeks

2Q. is linux not for Design verificaiton training?

  1. 4 months
    Verilog, SV, UVM
  2. DFT
    Input: RTL code or Gate level code
    Output:
    1. Test vectors
      test_vector1: 10101010101111000101010101010101101010100101010
      test_vector2: 000010110101010101111101010101010010101010101010001
    2. Gate leve code or RTL code updated for self testing logic
      o which will help detect any manufacturing defects in the design.
  3. Functional verification
    o main role: catch bugs in the design
  4. is rtl designing and design verification is same?
    • different
  5. what about the projects for DFT?which tool is using
    o IRIS
    o Understand whole DFT flow

8Q. if possible, can yobugsu show us how this error is being detected now, using testbench and tool?

9Q. what are the other scope for DESIGN Varification Engineer .
o to catch the design bugs

10Q. It means DFT before manufacturing & Design Verification engg after manufacturing…
o both happens before manugaturing

11Q. is tools or softwares are same in company which we are using in labs?
o yes

12Q. RTL design is verifying or working on code and dft means working on TB sir?
o No
o DFT doesn’t involve any TB at all(except for when you run simulation)

13Q. should we be preparing for verilog seperately or sessions are enough sir.
o Verilog 4-5 sessions are enough

14Q. every domain has its importance but to compare btw DV & DFT which is better and wil have good growth

15Q. There is an UVM course for 8 weeks on the website. Should we take up that course if we get into UVM? Since this course also includes UVM in syllabus, is it sufficient?
o UVM = UVM Essentials + UVM Advanced

  1. text editors
    GVIM
    notepad++
    kedit
    emacs
  2. what is Verilog?
    o Hardware description langauge
    Why Verilog is required?
    why modelsim is required?
  3. 3 bit up counter (time taken in digital session: 30 minutes)
    0 -> 1 -> 2…7->0..
    truth table
    k-maps
    boolean expression
    draw the circuit
    implement the circuit
  4. 20 bit up counter (time taken in digital session: 30 minutes)
    0 -> 1 -> 2…7->0..
    truth table
    k-maps
    boolean expression
    draw the circuit
    implement the circuit

truth table entries: 2**10 = 1024 rows
kmaps = 1024 boxes in kmap
it may take 1 full day to do this.

20Q. What is verilog AMS?
AMS: Analog mixed signal

Verilog : Digital design
Analog compoennts coding needs Verilog AMS langauge
  1. Basic coding examples of Verilog
    o combinational => initial 1 week on this
    o Multiplexor, decoder, encoder
    o full adder, half adder
    o realizing gates usng other gates
    o subtractor
    o priority encoder
    o comparator
    o ALU
    o sequential => 4 weeks on this
  2. half adder
  3. Verilog supports 4 styles of coding the designs
    o data
    o gate level
    o behavioral
    o it is very close to English.
    o switch level (redundant)

SESSION#2

  1. need for a new langauge?
    o concept of time => nature of sequential circuits
    o concept of structure
    o concept of concurrent running processes
    o typing on KBD
    o online session
    o presentation is displayed to Projector
  2. Why we can’t use Hindi for Hardware description?
    o there are no compiler for Hindi
    o there are no synthesis tool for Hindi
    o Hindi has 5000 words
    o Verilog has only 100 words
  3. Mux
    behavioral => always
    data flow => assign
    gate level => gates
  4. initial begin
    a = 10; //giving value of 10
    //a is registering value of 10 20; //20 units(20ns) of delay a = 40; //giving value of 40
    end
  5. why we are store value in register?
  6. i0 = $random; //$rnadom : generates a random number
    $ : Langauge provided task/function
    random: generating a randon number
    $random: generates a 32 bit random number

include “stdio.h” => printf, scanf

7Q. why input as reg and output as wire ??

  1. wire, reg
    wire => electrical wire
    o till the time electricity supply is there, they will have the value.
    reg => battery based bulbs
  2. vlib work => library creation
    vmap work work => library mapping
  3. I think notepad++ is easy to use other than GVIM

11Q. When we create a new folder for different project. Is it required to define vlib…
o modelsim => yes
o questasim => no

12Q. in the design module we are making the output as reg and input as wire …..why output is reg(why we are storing it)

13Q. why we need these i.e vlib and vmap …please explain
library: the way things are stored inside the tool

14Q. can we write design and TB in same .v file ?
– yes

15Q. in tb you are using `include statement is it mandatory?
o not mandatory

16Q. do we need to necessarily to take as “work”…or some other name
o not compolsory
o we can use some other librayr name also

17Q. $random genereates randon number, then how will know it is 0 or 1 it will be different apart from this. then how will work 2×1 mux?

  1. {i0, i1, sel} = $random; //$rnadom : generates a random number
    $random generates 32’b1010_1010_1100_1010_0010_1010_1110_1110

19Q.
why $monitor not at the bottom of first initial statement after repeat statement

20.
y = i0~sel | i1.sel
and, not, or, and

SESSION#3

materials

  1. inskill.in
  2. added to some group
    o whatsapp group
    o skype group
  3. access to recorded videos from live sessions
  4. access to all the ppts, assignments
  5. installed Modelsim tool and know how to use the tool
  6. Individaul GOogle drive link
    o Sreenivas
    o Digital
    o Verilog
    o ASGN1 => submit your solutions in to that folder
    o ASGN2 => submit your solutions in to that folder

revision:

  1. HA, FA using HA
  2. 2×1 mux, 4×1 mux using various abstraction levels

questions:

  1. theoretical
    o what is difference between vector and array
    reg [7:0] a; //Vector : all 8 bits stored in same address location
    reg b [7:0]; //Array : 8 bits stored in 8 different locations, one bit in each location
    analogy:
    vector: 8 family member in same house
    a = 8’b1011_0011
    a[0] = 1;
    a[1] = 1; //also posisble
    array: 1 member of each house, 8 continuous houses
    o post man comes, he want to give 8 post to each perion
    b = 8’b1011_0011; //not possibel in case of array
    o b rpresents 8 different address locations
    b[0] = 1; //possible
    b[1] = 1;
    b[2] = 0; so on
    reg [0:7] c;
    o reg [2:0] b [7:0]; //Array of 8 locations, each having 3 bits
    o 8 houses, each house having 3 people
  2. assignemtn specific
    o 8 bit HA
    o there won’t be any carry in
    o case and casex
    o why casex is used in priority encoder? why case doens’t work?
    case requires more lines of code. o if a=1 and b=0, both are one bit inputs and c is a 2 bit number the what is the instruction to concatenate a and b to c lik
    c = {a, b} //if we want a in MSB
    o why we use $random, how it works, and syntax
    o encoder using mux
    o how to implement code using case
    2×1 mux using case
    always @(*) begin
    case (sel)
    1’b0 : y = i0;
    1’b1 : y = i1;
    endcase
    end o where to use reg and where not to use
    – always or initial block, variables on LHS => declare them reg o while using case statement in 4x1mux,i had given default:y=1’bx, but in simulation it gives wrong answer sometime y
    o debug support session o please explain 4×1 using 2x1mux
    o Difference between using ifelse & case statements in behavioral design?
    o Can we declare different size vectors as same input? Like, input [3:0]a, [1:0]b;
    No
    o Can we use more than one module in same.v file?
    yes
    o does interchanging of input & output ports matter while defining itself sir?
    o no
    o How many times we can use $ monitor in a code
    o any number of times o always,initial,,begin,end
    o
    o what is differnce b/w variable nd reg??
    o Verilog don’t have anything called as variable o explain priority encoder
    o casex o 8×1 using only 4×1 using vector. [7:0]
    o o Question: When we use “inout” port? – PLease give example.
    o explain procedural block,nonprocedural block
    o what shouid be the default output combination for a encoder for both normal encoder and priority encoder
    o when delay is not used in repeat, will loop only once ? or will it complete all runs and then take the final value ?
    o in mux8x1 i had written code for 8x1mux using 2×1 mux but it gives correct ans for only one bit, i had tried for more than one bit it doesnot give correct ans..
    o in coding point of view how to code these things (basic gates design using mux) & there is one more qst in assgn1 (encoder&decoder using mux)
    o please explain some basic commands in theory of verilog programming
    o how to give $random in a vector
    o 8×1 using only 4×1 using vector. [7:0]
    o difference between display and monitor
    o in the design of encoder or mux which order we should follow while declaring inputs.. whether LSB should be first or MSB should be first?
    o explain blocing and nonblocking
    o data type in verilog
    o difference between initial ad always
    o Use of $random
    o explain concatenation style of implementation.
    o explain assign statement
    o various operators…
    o how to give a random input in vector
    o while declaring inputs for 8:1 mux should we prefer declaring individually or we go for vector?
    o Parameterizable full adder
    o Design encoder using gate?
    o explain significance of dataflow behavioral and gate level modelling, which one to use when?
    o which style of coding should we focus on.
    o why do we cant assign a value of wire to the output port?
    o explain diffrence between symbol & and && with example
    o gate level codeing
    o how to use circle before any statement?
    o How to write the “`include “for gate level , behavioral and structural
    o why $random gives only 0,1 why not choose other value
    o how reg, wire varies in 3 styles of modelings
    o 4-bit counter how to write logic
    o how can i judge which model is better for particular program? either data or behavioral or any other
    o explain instansiation of module
    o can we use assign for reg variable
    o What is the most efficient way of mapping?
    o difference between + and | operator
    o how we use assign astatement in sequential circuit
    o code 4:2 encoder using 2×1 mux
    o 4 cross 2 encoder using 2 cross 1 encoder how to implement o please explain everyting in sequence manner for verilog program so that we can solve every question from assignment…
    o will there not be theory session where you will explain everything in sequence?or do we have ask ques like this??
  3. when we use parameter in design, is it compolsory to use parameter in TB also?
    Yes.

3.
case, if, for, while, forever, repeat
o all these statemnts must be written only inside always or initial block.,

4
16 => Hexa, Binary, Oct or decimal?

  1. every programming langauge has if and case
    o in lanauges, case is implemented as ‘switch’
  2. always @(*) Only for combinational logic

7Q. where do we use single input and where do we use vector input?
o as much as posisble we always use ‘vector’

8Q. idfference betweeen
reg [3:0] i = 4’b1000;
reg[3] = 1
reg [0:3] i = 4’b1000;
reg[3] = 0
reg[0] = 1

  1. temparate details of Bangalore for 1 month
    real tempArray[29:0];
    real [29:0] tempvector; ==> not possible

10Q.
input [4:0]a;
input [4:0]b;

input [4:0] a, b; //both a, b are 5 bit variables
input a, [4:0] b; //this is not possible

11Q.
input [7:3] a; //possible
input [-7:-3] a; //possible
input [7:-3] a; //possible

  1. data_type array_name[index];
    integer intA[7:0];
    reg regArray[3:0];
  2. input a; //1 bit variable

14Q. Q Vector is also possible that define the temp of one one location ???
reg [31:0] temp;
temp is a integer, it needs 32 bit store

15Q. data types only for arrays? N not for vectors…
for vector, data type is compolsiry 1 bit variable only
reg or wire.

integer [3:0] a; //not possible
reg [3:0] a; //possible
wire [3:0] a; //possible
  1. case and casex
    priority encoder
    casex(in) //4’b1100, 4’b1001
    4’b1xxx : out = 2’b11;
    4’b01xx : out = 2’b10;
    4’b001x : out = 2’b01;
    4’b0001 : out = 2’b00;
    endcase
    o casex => case branch ordering is important
    o casex treats both x and z as don’t care is it possibel to do with case?
    o it is possible
    case(in) //4’b1100, 4’b1001
    4’b1000 : out = 2’b11;
    4’b1001 : out = 2’b11;
    4’b1010 : out = 2’b11;
    4’b1011 : out = 2’b11;
    4’b1100 : out = 2’b11;
    4’b1101 : out = 2’b11;
    4’b1110 : out = 2’b11;
    4’b1111 : out = 2’b11; 4'b0100 : out = 2'b10; 4'b0101 : out = 2'b10; 4'b0110 : out = 2'b10; 4'b0111 : out = 2'b10; 4'b0010 : out = 2'b01; 4'b0011 : out = 2'b01; 4'b0001 : out = 2'b00; endcase
  2. why we use $random, how it works, and syntax
    o to gneerate a random integer
    o integer is 32 bit size
    32’b…… (32 bits) o {i0, i1, i2, i3, sel} = $random; //$rnadom : generates a random number
    $rnaomd = 32’b1010_1100_1111_1100_0000_0101_0001_1101
    sel =
  3. use concatenation operator to swap two bytes
    reg [15:0] a, b;
    //we want to swap bytes of a and b
    b = {a[7:0], a[15:8]};
    a = 16’b1234;
    b = 16’b3412;
  4. 2×1 encoder using 2×1 mux
    o 2 bit encoder
    i1 i0 y
    0 0 x
    0 1 0
    1 0 1
    1 1 x
  5. 2×1 encoder using 4×1 mux
  6. 4×2 encoder using 4×1 mux
  7. initial is used in TB, always is used in design
  8. is strucural code same as gate level coding.
    • gate level coding is one sub aspect of strucural coding

25.
cd ../../.. => go 3 folders up

26
integer a;
reg [31:0] a;

SESSION#4

o 8x1 using only 4x1 using vector. [7:0]
    o 

o Question: When we use "inout" port? - PLease give example.
    o when design has inout port

o explain procedural block,nonprocedural block
    o procedural block: always, initial
        o procedural statements
        always @(posedge clk) begin
            a = 1;
            b = 10;
            #10;
            c = 5;
        end
    o continous assignments, structural coding

o what shouid be the default output combination for a encoder for both normal encoder and priority encoder 
    o default combination is xx

o when delay is not used in repeat, will loop only once ? or will it complete all runs and then take the final value ?
      a = 10;
      #10;
      repeat(10) begin
        a = a+1;
      end
      a = 20; //at 10 units, a=20

o in mux8x1 i had written code for 8x1mux using 2x1 mux but it gives correct ans for only one bit, i had tried for more than one bit it doesnot give correct ans..

o in coding point of view how to code these things (basic gates design using mux) & there is one more qst in assgn1 (encoder&decoder using mux)
    2 input XNOR using Mux
    a  b   y
    --------
    0  0   1
    0  1   0
    1  0   0
    1  1   1

    3 input XNOR using Mux
        - even number of 1's => 1
        - odd number of 1's => 0
    a  b   c    y
    --------
    0  0   0    1
    0  0   1    0
    0  1   0    0
    0  1   1    1
    1  0   0    0
    1  0   1    1
    1  1   0    1
    1  1   1    0


o please explain some basic commands in theory of verilog programming 
    o we will learn as part of presentaiton today

o 8x1 using only 4x1 using vector. [7:0]
    o answered

o difference between display and monitor
    o answered

o in the design of encoder or mux which order we should follow while declaring inputs.. whether LSB should be first or MSB should be first?
    o doesn't matter, any order you can follow
    nand g1(outptu_first, then_inputs); //coming from language


o explain blocing and nonblocking
o data type in verilog
    o reg, net
    o integer, real, time, realtime
o difference between initial ad always
    o initial used in TB coding
    o always used in design coding

o Use of $random
    o to apply random inputs

o explain concatenation style of implementation.
    o 

o explain assign statement
    o implementation similar to logic gates
        assign y = a & b & c;

o various operators...
o how to give a random input in vector
    o discused already

o while declaring inputs for 8:1 mux should we prefer declaring individually or we go for vector?
    o vector => redcues number of port names required
    s0, s1, s2 => sel

o Parameterizable full adder

o Design encoder using gate?
    o truth tbale => use k-mpas => boolean expression

o explain significance of dataflow behavioral and gate level modelling, which one to use when?
    o Behavioral => sequential logic implementation
    o Dataflow => combinational logic implementation
    o structural/gate level => if some modules are already present, use them to create bigger module
    o combination of all above styles is possible. 

o why do we cant assign a value of wire to the output port?

o explain diffrence between symbol & and && with example
    &, &&
    & : Bitwise and operator
    && : Logical and operator

    reg [-2:-5] a, b; //is also possible
    reg [3:0] c;
    a = 4'b1100;
    b = 4'b0001;
    c = a & b = 4'b0000  //bitwise ANDing
    c = a && b = what is logic of A & what of logic of B;
                = true_logic & true_logic = true_logic = 1

o gate level codeing 
    o 4x1 Mux using gates.

o how to use circle before any statement?
    o 

o How to write the "`include "for gate level , behavioral and structural


o why $random gives only 0,1 why not choose other value
    o $random gives a 32 bit random number
    32'b101010100101010101010101010 => Deciimal? Hexadecimal? all are possible

o how reg, wire varies in 3 styles of modelings
    o discused

o 4-bit counter how to write logic 
    o 

o how can i judge which model is better for particular program? either data or behavioral or any other
o explain instansiation of module

o can we use assign for reg variable 
    o No

o What is the most efficient way of mapping?
    o connection by name

o difference between + and | operator
    + : arithmetic operator
    | : OR operator

o how we use assign astatement in sequential circuit
    o we should not use.

o code 4:2 encoder using 2x1 mux


o 4 cross 2 encoder using 2 cross 1 encoder how to implement

What is the difference between these instantiation :
Mux dut(i,s,y) //this is possible
Mux dut( .i, .s, .y) //this is not possible
Mux dut( .i(a), .s(b), .y(c)) //this is not possible
TB has a variable, which is connected to i port of Mux

Why fullstop before each ports???

  1. code 4:2 encoder using 2×1 mux

y3 y2 y1 y0 a1 a0

0 0 0 0 x x
0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 x x
0 1 0 0 1 0
0 1 0 1 x x
0 1 1 0 x x
0 1 1 1 x x
1 0 0 0 1 1
1 0 0 1 x x
1 0 1 0 x x
1 0 1 1 x x
1 1 0 0 x x
1 1 0 1 x x
1 1 1 0 x x
1 1 1 1 x x

  1. tb.v
    include "4.v" include “1.v”
    include "2.v" include “3.v”
  2. can we implemente 4×1 mux behavior using C lanauge?
    o it is possible
    o any combinational logic(behavior) can be impelmented using C lanauge
    o where do we get limitation wtih C lanauge?
    o sequential cricuits can’t be implemented => requires clock => C lanauge doens’t have concept of clock.
    o C lanauge don’t have posedge and negedge
  3. reg [3:0] a;
    a is register 3 downto 0;
  4. distance 10 hours
  5. distance 10 kms

string name;
name = “verilog”; //” ” is called as string literals.
integer a;
a = 32’bpqr; //wrong: p,q,r are not valid binary literals

integer intArr[3:0] = 1,2,3,4; //wrong
integer intArr[3:0] = {1,2,3,4}; //correct => array literals
integer intArr[3:0] = [1,2,3,4]; //wrong

  1. why we need ‘x’ in simulations?
    o whenever DFF setup or hold time violation happens, output enters in to metastability state.
    o metastability means a state where we don’t know 0 or 1
    “I don’t know whether 0 or 1” => x
  2. hardware connections
    o during Verilog coding, connections can be two types.
    o a type of connection which needs to be continously driven
    o wire
    analogy: electrical wire
    o a type of connection which needs to be discretely driven
    o reg
    analogy: bulb with built in battery

SESSION#5

revision:

  1. hardware connections
    o reg
    o net
    o wire, wand, wor, tri

Agenda:

  1. scalar
  2. vector
    o vector copying
  3. array
  4. array of vector

Notes:

  1. Where tristate buffer is used
    o GPIO, I2C
    o where same ports need to behave as both input and output =>
  2. registers
    o where we need to register the value, hold it for some time, then we can change it. reg [5:0] a; //vector
    reg b; //scalar
    wire c; //scalar
    initial begin
    a = 10;
    #20; //holding(registering) the value of a to 10 for 20 units of time
    a = 50; //to hold value of 50, a should be atleast 6 bits size
    end
  3. intiial, always
    o variables on LHS of the statmeent => reg
  4. reg a;
    a = x is default value
  5. given a vector, how to get the size
    reg [9:6] wdata;
    magnitude[MSB-LSB]+1

reg [-3:-5] addr;
size = -3+5+1 = 3

reg [-5:-3] addr;
size = -5+3+1 = -1 => WRONG
size = magnitude(-5+3)+1 = 2+1 = 3

reg [-10:9] addr; //-10, -9, -8….9
size = magnitude[MSB-LSB]+1
MSB : -10
LSB : 9
= magnitude[-10-9]+1 = 19+1 = 20

reg [-5:5] addr;
-5-5 = 10 + 1 = 11

  1. how to declare a vector
    o LSB, MSB
    o name of the vector
    o type of vector(reg or net)
  2. declare a reg vector whose LSB is 5, MSB is 10, name is rdata
    reg [10:5] rdata;
  3. declare a net vector whose LSB is 7, SIZE is 11, name is wdata
    wire [17:7] wdata;
    wire [-3:7] wdata;
    -3-7 = 10 + 1 = 11 (size)

9Q. so the MSB and LSB given are for our reference ?

  1. declare a 5 bit net vector(addr), whose LSB is -2
    wire [2:-2] addr; //2,1,0,-1,-2
    wire [-6:-2] addr; //-6, -5, -4, -3, -2
  2. why we need vectors?
    • 4×1 mux
      module mux4x1(i0, i1, i2, i3, s0, s1, y);
      module mux4x1(i, s, y);
      input [3:0] i;
      input [1:0] s;
    • 2nd benefit
      module muxnx1(i, s, y);
      parameter N=16;
      parameter SIZE=$clog2(N);
      input [N-1:0] i; //16 bit vector
      input [SIZE-1:0] s; //4 bit vector
      same using scalar:
      module muxnx1(i0, i1, i2,…..i15, s0, s1…s7, y);
  3. I want to declare a clock
    reg clk;
    reg rst;
    reg temparature; //0 or 1 => hence not correct
    reg [7:0] temparature; //0 to 255
  4. ex, if processor can do 4 operations
    o write, read, reset, erase
    o oper
    reg [1:0] oper;
    2’b00 : Write
    2’b01 : Read
    2’b10 : Reset
    2’b11 : Erase
  5. name, direction, scalar, vector(size)

module processor(clock, reset, addr, wdata, rdata, wr_rd, valid, ready);
input clock, reset;
output [7:0] addr;
output [31:0] wdata;
input [31:0] rdata;
output wr_rd;
output valid;
input ready;
//we need to impelemt the code
endmodule

module memory(clock, reset, addr, wdata, rdata, wr_rd, valid, ready);
input clock, reset;
input [7:0] addr;
input [31:0] wdata;
output [31:0] rdata;
input wr_rd;
input valid;
output ready;
//we need to impelemt the code
endmodule

module memory(clock, reset, addr, wdata, rdata, wr_rd, valid, ready, data_o, data_i, addr_o);
input clock, reset;
input [7:0] addr;
input [31:0] wdata;
output [31:0] rdata;
input wr_rd;
input valid;
output ready;
output [7:0] data_o;
input [7:0] data_i;
output [7:0] addr_o;
//we need to impelemt the code
endmodule

  1. reg [31:0] addr;
    assign value in binary format
    addr = size’value
    addr = 32’b101001010101011010001010101010;
    addr = 32’hABCD_1237
  2. make all the bits of addr to x
    addr = ‘bx; //makes all bits of vector to ‘x’
  3. make all the bits of addr to z
    addr = ‘bz; //makes all bits of vector to ‘z’
  4. make all the bits of addr to t
    addr = it is not possible, since ‘t’ is not a valid thing
  5. make all the bits of addr to 0
    addr = ‘b0;
    addr = 0; //makes all bits of vector to ‘0’
  6. make all the bits of addr to 1
    addr = ‘b1; //WRONG
    = 32’b1 //WRONG => 32’b0000_00000…._0001
    = {32{1’b1}}; //Correct
  7. addr is decimal 200, size=15
    decimal format: addr = 15’d200
    decimal format: addr = 200
    hexadecimal format: addr = 15’hC8
    octal format: addr = 15’o310
  8. 357, size=14, data, assign in all 4 formats
    data = 357 //256+96+5
    Hexa: data = 14’h165
    Octal: data = 14’o545
    Binary: data = 14’b101100101
  9. Homework
    What EDA stands for?
    What are the steps involved in implementing a design using gates?
    What is meant by higher level description?
    How Hardware differs from a software?
    Why C/C++ are not suitable for hardware description?
    How Verilog represents concept of structure?
    How Verilog represents concept of time?
    How Verilog represents concept of concurrent running process?
    What is the IEEE standard for Verilog?
    How many IEEE Verilog versions are there?
    Why Verilog is preferred over VHDL?
    Write Verilog code of Synchronous DFF?
    Write Verilog code of active low reset Asynchronous DFF?
    Write Verilog code for 4X1 Mux?
    How to check if Verilog code is working as expected?
    Write Verilog code for 3 bit FA?
    What are various steps in Verilog code execution?
    What are various abstraction levels in Verilog?
    What is meant by Literals?
    What are the examples of Verilog literal value set?
    Why do we need ‘x’?
    Why do we need ‘z’?
    reg addr; is it scalar or vector?
    reg [3:0] valid? scalar or vector?
    represent 578 using 10 bit size in all radix format?
    reg [-3:3] vec_a, reg [7:1] vec_b, vec_a = vec_b, what is the mapping?
    if vec_b value is 125, what is vec_a[2]?
    what is octal equivalent of following?
    xxx, xzx, x0x, z0z, 1zx, zzz, 101
    What is the default radix if not specified?
  10. Size of LHS vector(vec_a) is smaller than RHS vector(vec_b)
    {i,s} = $random;
    {a,b,ci} = $random;
    //LHS: Smaller
    //RHS: Bigger, 32 bits in size
  11. Size of LHS vector(vec_a) is bigger than RHS vector(vec_b) reg [3:0] a;
    reg [31:0] b;
    a = 4’b1011;
    b = a;
    = 32’b1011;
  12. little more complex
    reg [3:0] a;
    reg [31:0] b;
    a = 4’bx011;
    b = a;
    = 32’bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx011;

SESSION#6

revision:

  1. Vector
    o what all ports are there
    o directions, size
    o how to declare the ports
  2. importance of vectors
  3. working with vectors
    o hwot o declare
    o how to initialize
    o how to copy one vector to anotehr vector
    o LHS vector smaller in size than RHS vector
    o LHS vector bigger in size than RHS vector
    o LHS vector equal to RHS vector size
  4. {a, b,c,d} = 32’h12345678;
  5. 4 bits: nibble
    8 bits: byte
    16 bits: half word
    32 bits: word
    64 bits: double word
  6. position values
    reg [33:0] addr = 34’h6383883232;
    what is addr[5:3]?
    what is addr[12:6]?
    what is addr[31:20]?
    what is addr[15]?
    what is addr[24:19]? 6’b110001

7.
reg [8:0] a;
a = -69 //how -69 will be stored in binary format
a[3:1]?

  1. homework
    reg [3:0] a, b, c;
    a=9, b=7, c?
    c = a*b;
  2. DFT
    o finding manufacturing defects
    o 5nm
    o Tool(Tessent, DFT advisor..)
    o ATPG
    o test pattern(test vector)
    o DFT engineer should know, how to add
    o tdi, tdo, clk in to waveform
    o analyze thse signals, check the behavior

10.
always @() begin
r = 3.5;
end

k=2.3

  1. below is correct
    module test;
    integer a = 10;
    wire b;
    assign b = a; //sir is it correct?
    //assign a = 20; //WRONG
    endmodule

12.
2.5 rounds off to 3
2.51 rounds off to 3
2.49 rounds off to 2

13Q. what is the format specifier to print integer and real in verilog?
integer: %d
real : %f

14Q. how to change time unit like by default ns then how to change it sec

15.
Clock
– frequency
– duty cycle
– jitter

  1. Clock TP=20ns
    to measure: 20ms
    count 20ms/20ns number of clock edges analogy:
    1 day time = 24 hours(Clock time period)
    to measure 720 hours => how many days to count = 30 (720/24)
    count 30 sun rises. => 720 hours
    sun rise: rising edge of clock
    sun set: falling edge of clock
    720 hours => total time to measure
    720 hours => count 30 sun rises

17Q. how do we know the time period of clk sir? is it given?
o given a clock frequency => we can get the time period
1GHz => 1ns TP

  1. Measure the number of clock required to count 1second using 50 MHz clock.
    o 50MHz => TP = 20ns
    numbers of clocks for 1 sec = 1 sec/20ns = 1/2010-9 = 1/210-8 = 108/2 = 5*107 = 50 million cycles
  2. Measure the number of clock required to count 1ms using 25 MHz clock.
    o 25Mhz => TP = 40ns
    o 1ms/40ns = 10-3/410-8 = 10*5/4 = 25000 cycles
  3. Measure the number of clock required to count 5us using 1 GHz clock.
    o 1 GHz => TP = 1 ns
    o 5us/1ns = 5000

SESSION#7

  1. Questasim : 1ns as default timestep
    modelsim : 1ps as default timestep
    `timescale 1ns/1ps
  2. Clock generation
    S1 : Clock of 100Mhz, 10ns TP
    S2 : Clock of User provided frequency
    S3 : Clock of User provided frequency by using user specific time precision
    S4 : Clock of User provided frequency, user provided duty cycle
    S5 : Clock of User provided frequency, user provided duty cycle and user provided jitter
    S6 : generate another clock with 90% phase difference from original clock
    TP = 360 degress
    TP/4 = 90 degress
    S7 : generate another clock with 90% phase difference from original clock
  3. If I can go 10ft in 1 step => timestep=10 feet
    how many steps required = 1 step
    If I can go 1ft in 1 step => timestep=1 feet
    how many steps required = 10 steps 10 feet : simulation time
    how much you will go in each step => time step
    time precision?
  4. default time scale of tool
    `timescale 1ns/1ns
    timestep/timeprecision
    timestep has no relation to clock
    o completely tool internal concept
  5. high time
    TP*duty_cycle/100 low_time
    TP*(100-duty_cycle)/100
  6. Jitter
    exp_tp = 5ns
    act_tp = 4.88ns
    variation % = 0.12/5 *100 = 12/5 = 2.4% variation => 2.4 jitter

7.
500Mhz clock with 5% jitter?
475 to 525

  1. Update your resume with below project
    project#1
    Title: CLock generation for user provided frequency, duty cycle, jitter and phase.
    Description: As part of this project, clock is generated for various parameters provided by the user.

45 degress phase:
assign #(TP/8) clk_1 = clk;

  1. $urandom_range(100,200);
    • it generates a number between 100 to 200

$urandom_range(-100,-200);
– it generates a number between -100 to -200

10.
wire, reg, real, integer, time, realtime => singular

non-singular : they represents multiple values
integer intArr[3:0]; //how many values are there? 4 => non-singular

reg [7:0] a; //singular
reg [7:0] abc[3:0]; //non-singular

  1. array in any lanauge => all those concepts will apply in Verilog also

12.
reg vec[31:0];
it will require 32 locations to store this array.
each location stores 1 bit.

reg [3:0] vec [31:0];
WIDTH DEPTH


  1. reg [WIDTH-1:0] mem [DEPTH-1:0]
    SIZE_OF_MEMORY = DEPTH * WIDTH

Kilo = 1024
Mega = Kilo * Kilo = 1024 * 1024
Giga = Kilo * Mega = 1024 * 1024 * 1024
Byte = 8 bits
1KB = 1024*8 bits

1024 = 2n => n = 10 Kilo = 210
Mega = 220 Giga = 230
Byte = 2**3 bits
1KB = 1Kile Byte
1Kb = 1Kile bit

Mega/Kilo = 220/210 = 210 Convert everything in to 2 format

  1. Decalre a memory(name: mem), Size=1KB, DEPTH=128
    SIZE=213 bits DEPTH = 27
    WIDTH = 213/27 = 2**6 = 64 reg [63:0] mem [127:0]; //1KB memory
  2. Decalre a memory(name: mem), Size=2kb, WIDTH=16
    size = 211 bits WIDTH = 24
    DEPTH = 2**7 = 128
    reg [15:0] mem[127:0]
  3. reg [63:0] mem [7:0]
  4. how to work with array
    declare an integer array of size 10
    intArr
    declare anotehr integer array, copy 1st array elements to 2nd array
    then compare both arrays

18.
for (i = 0; i < SIZE; i=i+1) begin
end

  1. array
    • how to declare array?
    • how to print array?
    • how to initilize array?
    • how to assign random values to array?
    • how to copy one array to anotehr?
    • how to compare one array with anotehr?

SESSION#8

revision:

  1. array
  2. clock generation
  3. memory
  4. operators
    o arithmetic
    o logical
    o equality

agenda

  1. hierarchical modeling
  2. operators

questions

  1. notes:
  2. April : 30 days
    Bangalore temp: 32 to 37
    get the average temp:
  3. hierarchical modeling
    o structural modeling
    o Full adder
  4. implement 4-bit full adder using 1-bit full adder
  5. what is meant by run time
    initial begin
    for (i = 1; i <=5; i=i+1) begin
    sum = sum + i;
    end
    end

5.
fa_nbit dut(a, b, ci, s, co); //dut : design under test
defparam dut.WIDTH = WIDTH;

6Q.
can u explain overriding width & depth concept???

  1. function
    o what is a function?
    o why is it required?
    o how to declare and how to use?
  1. function to add two integers and return the sum

a,b and p,q are different is this the syntax

9Q. for more than one output like sum amd carry do we need more than one function?

10Q. is return type mandatory
yes

11Q. line 9 input is taking reg. Is it because the arguements are being passed from initial block ?

12Q. carry is name of function why u assigining the total in carry

SESSION#9

  1. We have a register which is 16 bits, we want to always write [7:4] as always 4’b1111, irrespective of other bit values, how can we implement this using bitwise operators
  2. clock phases
    60 degrees
    1 complete TP = 360 degrees
    360 => TP
    180 => TP/2
    90 => TP/4
    60 => TP/6 initial begin
    clk = 0;
    forever #(TP) clk = ~clk;
    end
    initial begin
    #(TP/6.0);
    clk1 = 0;
    forever #(TP) clk1 = ~clk1;
    end assign #(TP/6) clk1 = clk;
    //anytime clk changes, clk1 will get updated after TP/6 time
  3. Same Operator symbol: different meanings
    & what all possible operators used &

4.
while clock phase shift I increased the duty cycle upto 80 and my output waveform got stuck at 1 but when I changed it to 50, I got the output waveform. What is the mathematics behind it sir?

  1. when to use reg, net, real
    real we use when we need to floating values.
    reg used when we need to register values
    net used when we need to continous driving behavior

6.
real r;

  1. could you please explain how we can design 512×8 memory using 256×4 (logic part)
    create 2 x 2 structure
    port connection is important

8Q. could you please show if there is any way were we can concatenate the inputs & get the o/p through only 5 mux’s instead of 10 mux’s for 4:2 encoder using 4×1 mux?
4×2 Encoder
how many outputs: 2 outputs A0, A1
A0 : requires 5 4×1 Mux’s
A1 : requires 5 4×1 Mux’s

Encoder truth table:

i3 i2 i1 i0 A1 A0

0 0 0 0 x x
0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 x x
0 1 0 0 1 0
0 1 0 1 x x
0 1 1 0 x x
0 1 1 1 x x
1 0 0 0 1 1
1 0 0 1 x x
1 0 1 0 x x
1 0 1 1 x x
1 1 0 0 x x
1 1 0 1 x x
1 1 1 0 x x
1 1 1 1 x x

9Q. how to add elements of array

10Q. Regarding Seeds: While gernerating random numbers with seed, if we print seed value along with random number it keeps changing. Seed number does not remain constant. Can you explain?


  1. while display the array
    $monitor(“a[%d]=%d”,i,a[i]);

What is the use of i after closing double inverting comma???

  1. clock generation

13.
assign #5 clk=!clk;
assign clk=#5 !clk;

  1. can you explain how to include and change parameter in run.do file
    o this is not possible in run.do

15Q. I tried to assign real output in design file, and supply input values from TB and print output value. but it shows only integer and not decimal value. I assigned output as real. I can share code please identify mistake?
o real ports is not possible in Verilog module
o get as bit vector, convert bit vector to real number

    real r;
    reg [63:0] vec;
    vec = $realtobits(r);

16Q.
is it necessary to pass decimal values from run.do and write %0d in $value$plusargs ….can’t we use %b in $value$plusargs or binary values in run.do ??

17Q. is if else possible inside always @(*) block sir?
o possible

18Q.
if we have declared a parameter size=10; can write data=size’b1;

19Q. what if in run.do no of bits are less than size of variable

20Q>
module top;
reg i;

initial
begin
for(i=1;i>=0;i=i-1) begin //i=i-1
$write(“1-2-3-“);
count = count+1;
end
end

initial begin
#50;
$finish;
end
endmodule. cant get out of the infinite loop

  1. can we use genvar concept in testbench sir?
    o possible initial begin
    genvar i;
    //not possible
    end

22.
reg signed i; // can take only signed values
signed concept is not there in Verilog

  1. what does $write does sir?
  2. !, ~

25.
reg a;
reg b;
a | b is not same as a + b
a = 1, b = 1
a | b = 1
a + b = 10 (results in carry)

  1. bitwise
    a, b, c : 8 bit variables
    a = 79; b = 54; c = a & b; c?
    a = 64+15 = 0100_1111
    b = 32+16+4+2 = 0011_0110
    c = a & b = 0000_0110 a = -21, b = -57, c = a & b
  2. difference btw arithmetic shift and logical shift
    o this feature is not supported in Verilog
  3. Hoemwrok
    a = b << c;
    in above, what is operator and what are operands?
    how shift operator makes multiplication easier to implement?
    what is the difference between logical not and bitwise inversion?
    a = -1, b = 1, c = a && b; what will be c?
    a = -1, b = 1, c = a & b; what will be c?
    size needs to be provided, assume integers.
    a = -7, b = 11, both are integers, what is a & b?
    real a; integer b; real c;
    a = 3; b = 10; c = b/a; what will be value of c?
    reg [5:0] a; reg [-2:-1] b; reg [5:0] c;
    a= 95;
    b = 69;
    c = a & b; what will be c?
    c = a | b; what will be c?
    How unary reduction operators make vector analysis easier?
    how the operator usage differs between vectors and arrays?
    We have a register which is 16 bits, we want to always write [7:4] as always 4’b1111, irrespective of other bit values, how can we implement this using bitwise operators
    List down various types of operators in Verilog
  4. a = 25;
    c = a>>2; //25/4 = 6.25 => round off to lower integer = 6

a is 8 bit reg vector
a = -25;
c = a>>2; //it will become very big number

30.
reg [3:0] a, c, d;
reg [4:0] b, e, f;
{a,b,c,d,e,f} = 32’h1234_5678;

31.
c = (a > b);
a = 4’b1010; b = 4’b10z0; => c will be x
a = 4’b10z0; b = 4’b10z0; => c will be x
a = 4’b1000; b = 4’b1010; => c will be 0

a = 4’b1010; b = 4’b00z0; => c will be x

  1. ternary : 3 operands
    a = b == 10 ? c : d;

33.
if (a+b > c) p = 10;
else if (d > e) p = 20;
else if (g+h == i) p = 30;
else if (k-l == m) p = 40;
else p = 50;

p = (a+b > c) ? 10 : (d > e) ? 20 : (g+h == i) ? 30 : (k-l == m) ? 40 : 50;

  1. b = 10, c = 20, d = 30
    a = b + c * d; a ? 610

if I want addition first, then multiplication?
a = (b + c) * d; a ? 900

35.
module tb;
integer b,c,d,e, f, g;
integer a;
initial begin
b = 100;
c = 200;
d = 10;
e = 20;
f = 5;
g = 2;
a = bc/de;
$display(“a=%0d”,a); //40000
a = bc/de/fg; $display(“a=%0d”,a); //16000 //my requirement : divide whole thing with (fg)
a = bc/de/(f*g); //4000
$display(“a=%0d”,a); //4000
end
endmodule

SESSION#10

  1. 3797 97(32+4+1)
    97<<5
    97<<2
    97 no shift

Add all 3

97 = 110_0001
97<<5 = 110000100000
97<<2 = 110000100
97 = 1100001
——————
1110_0000_0101

        1+4+512+1024+2048
  1. statements inside process will run sequneitally => compolsory

3.
assign {c, s} = a+b+ci;
LHS : concatenation of scalar net and vector net.

4.
initial clk = 0;
always #5 clk = ~clk;

5.
always clk = ~clk;
o 0 delay loop
o 0/0 relation

6.
always @(posedge clk)begin
if(reset==1) begin
{n1,n2,y}=1’b0;
else
begin
n1<=a;
y<=n1&b;
end
end

7.
always@(posedge clk)begin
if(res == 1)
Y<=0;
else
Y<=b&w;
end

always@(posedge clk)begin
if(res == 1)
w<=0;
else
w<=a;
end

  1. non-blocking statemnet
    • when this statemnet is happening, it doesn’t block the next statement

SESSION#11

questions

  1. can we implement gate level modelling in always block?
    o always @(posedge clk) begin
    a = b & c;
    and u1(a, b, c); //not possible
    end
  2. why nonblocking statement is used in sequential ckt.
    o immeidate output of the previous statement, we don’t want to cosnider.
    o we want to sampel the value just before the +edge of clock.

always @(posedge clk) begin
q1 <= d;
q2 <= q1;
q3 <= q2;
end

always @(posedge clk) begin
//there is no dependency in below variables
q1 = d;
p = r;
t = u;
end

3.
reg A[0+:8]; what does it signifie?
reg A[0:8];


  1. I’m getting wrong output so please check my code , which belongs to 21st question of Assignment-7

5.
explain the Multi-cycle path concept ? Is it we write multiple statements inside the always end block? Clarify it.
always @(posedge clk) begin //clk TP=10ns
s1; //a = b + c; Adder => Logic gates => transistors(MOS, FinFET)
//7ns
s2; //6ns
s3; //8ns
//21ns
end

6.
module test;

wire [32:0] y;
real a=14.4;

//assign y = a;

initial
begin
$display(“y=%f y=%b y=%d”,y,y,y);

30;

end

endmodule…………when i am uncommenting assign the value of y is printing as x ….rather it should be z as its a wire

7.
please explain 4x1mux using gate primitives with delays.

8.
do we need to follow any standard book also, or the ciricullum here is enough?

9.
module im(rst,clk,a,b,c,y,w);
input a,b,c;
input rst,clk;
output reg y,w;
always@(posedge clk)//synchronous reset
begin
if(rst)
begin
y=0;
w=0;
end
else
begin
y=a&b;
w=~c;
end
end
endmodule

  1. Defining a variable as reg, does not always infer DFF. Write an example to prove this.

module top;
reg s, co;

always @(*) begin
{co, s} = a + b + ci; //FA
end
endmodule

11.
wire [7:0] a;
a = -20; //236

wire [8:0] a;
a = -20; //492 (512-20 = 492)

wire [31:0] a;
a = -20; //(2**32-20 = )

  1. Print pascal traingle
  2. IRQ
    always @(irq) begin
    int0 = 0; int1 = 0; int2 = 0;
    case (irq)
    3’b100 : int2 = 1;
    3’b110 : int2 = 1;
    3’b101 : int2 = 1;
    3’b111 : int2 = 1;
    3’b011 : int1 = 1;
    3’b010 : int1 = 1;
    3’b001 : int0 = 1;
    default : $display(“no interrupt”);
    endcase
    end

//using casez
always @(irq) begin
int0 = 0; int1 = 0; int2 = 0;
casez (irq)
3’b1?? : int2 = 1;
3’b01? : int1 = 1;
3’b001 : int0 = 1;
default : $display(“no interrupt”);
endcase
end

SESSION#12

Questions:

  1. integer array vs reg array?
    integer intArr[9:0];
    reg regArr[9:0];
    common:
    – both takes 10 locations
    difference:
    – intArr will store 32 bits in each location
    – regArr will store 1 bit in each location
  2. pascal triangle
  3. please explain about default connection in port connections
    • any varibale on the LHS of procedural statmenet is ‘reg’
    • any other varibale is always a wire.
    real is reg based variable
    integer is reg based variable
    time is reg based variable

Notes

  1. pipelining
    • concept used in processor for increasing instruction execution speed
      o ex: processor can execture 10 instrctions per second without pipelining
      o ex: processor may execture 25 instrctions per second with pipelining 45+98
      97+25
      17+987
    • pipelining involves dividing the combinational logic in to smaller combinational logic by separating them using Flipflops.
  2. Verilog programming guideline
    • code combinational logic separately
    • code sequential logic separately

3Q. we give only one number as freq & do the req. calculation for time period how wil the simulator know we’re feeding certaing Mhz or Ghz as input?
– our assumption: User is giving input as MHz


  1. $display = $write + \n

5.
SV
vsim tb -sv_seed 40490

6.
seed for $urandom_range(seed)? not possible

I want to generate 10 random numebr btween 100 to 150 based on a seed

SESSION#13

assignment 8, Q21-d
assignment 8, Q14
assignment 8, Q12
explain %m
$display(“s=%m”,s); //tb0.0
value, also from where this display is called from.

Q19 do we have to define modules for all four combinational circuits and then use flip-flops in between?

can we use task in both module and testbench?
o yes
o design: task should be simple

task drive_mem();
begin
    @(posedge clk); //this is non-synthesizable
    #10; //this is non-synthesizable
end
endtask

Notes:

  1. What is the impact of using very small timestep i. `timescale 1ps/1ps ii. How simulation will be impacted due to this?
    1. How simulation slows down due to very low time step.

Analogy:
– ground floor -> 1st floor (10 Feet)
– my each step is 1 feet => how many steps it will take = 10 steps (10 sec)
– my each step is 1cm feet => how many steps it will take = 300 steps (won’t be 300 sec, atleast 50 sec)

2.
module top(input real r); //not possible
module top(input [63:0] vec); //possible
r = $bitstoreal(vec);

3
module tb;
parameter LSB=2;
parameter WIDTH=64;
reg [LSB+WIDTH-1:LSB] vec1;
initial begin
$display(“vec1=%b”,vec1);
$display(“vec2=%b”,vec2);
$display(“vec3=%b”,vec3);
end
endmodule

  1. institute.grnd_floor.office_room.table.laptop => XMR (Cross module refrence)

Mumbai:
karnataka.Bangalore.Horamavu.institute.grnd_floor.office_room.table.laptop => XMR (Cross module refrence)

Inside the institute:
grnd_floor.office_room.table.laptop => XMR (Cross module refrence)

SESSION#14

Questions:

  1. Implement Verilog code of 3 stage synchronizer.

always @(posedge clk2) begin
q1 <= din;
q2 <= q1;
q <= q2;
end

  1. module top;
    a a_inst(); initial begin
    a_inst.b_inst.write_tx.count = 10;
    $display(“a_inst.b_inst.write_tx.count = %0d “, a_inst.b_inst.write_tx.count);
    end
    endmodule

module a;
b b_inst();
endmodule

module b;
task write_tx();
integer count;
begin
end
endtask
endmodule

3Q. when will we start with project sessions?
– we will complete the test. We will egt the scores. Based on scores we will decide who will join project sessions. Then we will start.
60%, MCQ

4Q.

  1. k.Writing the if-else statement with complete check
    i. Binary encoder if not coded with complete input vector check can result in unintended circuit.
  2. Implement the proper style of coding this

5Q.
what is a full case and parallel case statement?

  1. ?
    casex => x and z are don’t care
    or casez => only z is don’t care
  2. total quesitons and timings
    o 100 questions
    o Wednesday -> Sunday, 2.5 hours
    MCQ
  3. can we take two outputs in primitive table?
    primitives only support one output
  4. validation job role
    o Intel
    o pre-silicon validation ==> Functional verification(RTL simulations done using Questa/VCS/NCSIM)
    o post-silicon validation => once Chip is manufactured, we check that by means of tester and test patterns.
    o otehr companies
    o validation => PSV

SESSION#15

  1. assgn 8 …ques23 ….part b ……can you please check my answer is it correct or not …………………………. if($value$plusargs()) //it is used as a system function bcoz function returns the value and that value can be used as the condition of if statement .
  2. Assignment 8 question number 19
  3. Task?
    o task is required wherever delay is involved
    o we want to write to a memory
    o write happens at +edge of the clock
  4. please explain file handling tasks like $fopen, $fmonitor once again

5.
Assignement 9, Q6_vii $ator

5.
many time glitch is coming in flipfliop example so how to remove

6.
explain difference between ifdef,ifndef compiler directives

7 is if(i==4’b01??) is allowed like in casex.
casex we can use 4’b01??
if condition, not allowed to use ?

  1. PLI and VPI
    o PLI : Programming language interface
    o VPI : Verilog programming interface

PLI and VPI are about ‘how to call a function present in C program from Verilog code’
o we can’t directly call that function, since it is present different langauge or code.
o we define a system task, which uses $calltf to call teh C function
system_task call_add();
$calltf(add); //add funciton is present in C program
$call_add(); //is done from Verilog code.

o Code execution:
    gcc test.c
    vlog sample.v
    vsim -so test.o work.top
  1. inter and intra delay statements are not syntheizable.
    o only used for simulation purpose.
    major difference:
    o RHS variable sample in case of inter delay statement happens after the delay
    o RHS variable sample in case of intra delay statement happens before the delay
  2. Defining a variable as reg, does not alway infer DFF
  3. test
    o 5PM today
    o Sunday 8PM

12.
$countone $onehot,$onehot0

reg [9:0] vec;
vec = 10’b10_1111_0001;
$countones(vec); => 6
$onehot(vec) = 0 => more than one bit is ‘1’

$onehot => check if only one bit is ‘1’
$onehot0 => check if at max one bit is ‘1’(no 1’s or 1 ‘1’)

Teacher is an important part of anybody's education.

I completed my post graduation in 2005. During my school and College, I always had difficulty coping up with things in classroom. But my Telugu teacher Mr. Hussain Budde during my 7th class , I used to enjoy his way of teaching, way he used to engage students by teaching lessons as stories. After that, I never found any teacher who kept sessions so much engaging. I don't want to blame my teachers, I always felt they could make sessions more engaging. I always had to spend time outside class hours to cope up with every minute of classroom session.

I as a teacher, I adopt a style of teaching which keeps session engaging and ensures that students give 100% focus on the session. I always wanted to be that one teacher, whom my students will remember for lifetime. I am making sure that, rest of trainer's also follow same.

I want your 6 months of education at VLSIGuru to be among your best learning experiences. We at VLSIGuru will do our best to make this a memorable time.

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