Implement Verilog code print prime numbers till user provided input using for loop
Read user input using $value$plusargs
Do the same using while loop
Do not start writing the code, first focus on coming up with algorithm.
What is algorithm?
Convert algorithm to Verilog code.
Generate random number for array (example of how to use for loop)
Declare an integer array of 10 size
Assign random values between 40 to 49 to the array elements
Repetition allowed
Use $urandom_range
Assign unique random values between 40 to 49 to the array elements
It means no repetition of numbers in the array
Implement unique random example for array size of 20, values between 40 to 59
How many statements in below code?
forever #10 clk = ~clk;
Why begin end not used?
What if we need to run multiple statements in forever loop, what is required?
This will apply for every procedural block
Casez
List down practical interrupt handling based use case on how we can give priority to specific interrupts.
Int2 > int1 > int0
How to use casez for this requirement.
Casex
Give a practical use case of casex
How many abstraction levels are there in Verilog, what are those?
Write a Verilog program for interchanging two numbers
Using a temporary variable
Without using a temporary variable
Try doing without non-blocking in two different initial blocks.
Both will take same number.
The output will vary based on how we place the initial blocks.
Implement using non-blocking
How non-blocking helps.
Understand the significance of temporary variable automatically created by non-blocking statement.
Explain what is race condition. What is the definition of race condition.
Using an example
What is difference between blocking and non-blocking statements.
How many Flipflops does below code infer
reg Q1,Q2,Q3;
always @(posedge clk) begin
Q1 = d; //Q1 gets updated immediately with value of d
Q2 = Q1; //Q2 gets updated immediately with value of Q1(i.e value of d)
Q3 = Q2; //Q3 gets updated immediately with value of Q2 (i.e value of d)
end
How many Flipflops does below code infer
reg Q1,Q2,Q3;
always @(posedge clk) begin
Q1 <= d;
Q2 <= Q1; //will use old value of Q1, not the updated one
Q3 <= Q2; //will use old value of Q2, not the updated one
End
Run simulation for above examples(both blocking and non-blocking) and analyze the waveform for Q1, Q2 and Q3.
Generate d value with random delay between 10 to 30 units, repeat 30 statement
Above blocking and non-blocking examples, try atleast 5 combinations in each with different order of statements.
Figure out number of FFs required, check this against the waveform.
Run and analyse the waveform.
In non-blocking, changing the order has no difference.
Explain this scenario, why it is working like this.
Always block
If sensitivity list has posedge or negedge, then use non-blocking assignments
If sensitivity list doesn’t have posedge or negedge, then use blocking assignments
Justify these two statements.
Implement multiple gates logic using always with non-blocking statements, run the code
Analyse the output
Run same example with blocking statement. Compare both results.
How many Flipflops does below code infer
reg Q1,Q2,Q3, a, b;
always @(posedge clk) begin
Q1 = d; //Q1 gets updated immediately with value of d
Q2 = a; //
Q3 = b; //
End
Above example, order of placing the statements won’t matter at all. Explain?
Explain what is Synthesis?
List down 10 synthesizable Verilog constructs
List down 10 non-synthesizable Verilog constructs
How many Flipflops does below code synthesize to?
Wire a, b, cin;
always @(posedge clk) begin
{c,s} = a + b + cin;
end
If s is 4 bit variable.
Draw the synthesized output diagram.
What is synthesis output?
always @(posedge clk) begin
y = a & b; //y gets updated immediately
z = x & y; //updated value of y is used for calculating z
end
Explain pipelining
Take a combinational logic of 150ns delay
5 inputs processing takes 750ns
Divide the combinational logic as 40,40,35,35
3 FF stages added in between
Now 5 input processing will take 380ns
Assuming minimum clock period required is 50ns
FF setup is 10ns, assumption.
Write Verilog code for Pipelining
Assume comb_1, comb_2, comb_3, comb_4 functions available for the 4 stages of the combinational logic.
We need to use 2 always blocks.
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