1. Procedural statements
1. Implement 4×1 Mux using if else
1. Implement 4×1 Mux using case
1. Implement Verilog code print prime numbers till user provided input using for loop
1. Read user input using \$value\$plusargs
1. Do the same using while loop
1. Do not start writing the code, first focus on coming up with algorithm.
1. What is algorithm?
1. Convert algorithm to Verilog code.
2. Generate random number for array (example of how to use for loop)
1. Declare an integer array of 10 size
1. Assign random values between 40 to 49 to the array elements
1. Repetition allowed
1. Use \$urandom_range
1. Assign unique random values between 40 to 49 to the array elements
1. It means no repetition of numbers in the array
1. Implement unique random example for array size of 20, values between 40 to 59
3. How many statements in below code?
1. forever #10 clk = ~clk;
1. Why begin end not used?
1. What if we need to run multiple statements in forever loop, what is required?
1. This will apply for every procedural block
4. Casez
1. List down practical interrupt handling based use case on how we can give priority to specific interrupts.
1. Int2 > int1 > int0
1. How to use casez for this requirement.
5. Casex
1. Give a practical use case of casex
6. How many abstraction levels are there in Verilog, what are those?
7. Write a Verilog program for interchanging two numbers
1. Using a temporary variable
1. Without using a temporary variable
1. Try doing without non-blocking in two different initial blocks.
1. Both will take same number.
1. The output will vary based on how we place the initial blocks.
1. Implement using non-blocking
1. How non-blocking helps.
1. Understand the significance of temporary variable automatically created by non-blocking statement.
8. Explain what is race condition. What is the definition of race condition.
1. Using an example
9. What is difference between blocking and non-blocking statements.
10. How many Flipflops does below code infer
1. reg Q1,Q2,Q3;
1. always @(posedge clk) begin
1. Q1 = d;  //Q1 gets updated immediately with value of d
1. Q2 = Q1; //Q2 gets updated immediately with value of Q1(i.e value of d)
1. Q3 = Q2; //Q3 gets updated immediately with value of Q2 (i.e value of d)
1. end
11. How many Flipflops does below code infer
1. reg Q1,Q2,Q3;
1. always @(posedge clk) begin
1. Q1 <= d;
1. Q2 <= Q1;  //will use old value of Q1, not the updated one
1. Q3 <= Q2; //will use old value of Q2, not the updated one
1. End
1. Run simulation for above examples(both blocking and non-blocking) and analyze the waveform for Q1, Q2 and Q3.
1. Generate d value with random delay between 10 to 30 units, repeat 30 statement
12.  Above blocking and non-blocking examples, try atleast 5 combinations in each with different order of statements.
1. Figure out number of FFs required, check this against the waveform.
1. Run and analyse the waveform.
1. In non-blocking, changing the order has no difference.
1. Explain this scenario, why it is working like this.
13. Always block
1. If sensitivity list has posedge or negedge, then use non-blocking assignments
1. If sensitivity list doesn’t have posedge or negedge, then use blocking assignments
1. Justify these two statements.
14. Implement multiple gates logic using always with non-blocking statements, run the code
1. Analyse the output
1. 1. Run same example with blocking statement. Compare both results.
15. How many Flipflops does below code infer
1. reg Q1,Q2,Q3, a, b;
1. always @(posedge clk) begin
1. Q1 = d;  //Q1 gets updated immediately with value of d
1. Q2 = a; //
1. Q3 = b; //
1. End
1. Above example, order of placing the statements won’t matter at all. Explain?
16. Explain what is Synthesis?
1. List down 10 synthesizable Verilog constructs
1. List down 10 non-synthesizable Verilog constructs
17. How many Flipflops does below code synthesize to?
1. Wire a, b, cin;
1. always @(posedge clk) begin
1.                 {c,s} = a + b + cin;
1. end
1. If s is 4 bit variable.
1. Draw the synthesized output diagram.
18. What is synthesis output?
1. always @(posedge clk) begin
1.                 y = a & b;  //y gets updated immediately
1.                 z = x & y;  //updated value of y is used for calculating z
1. end
19. Explain pipelining
1. Take a combinational logic of 150ns delay
1. 5 inputs processing takes 750ns
1. Divide the combinational logic as 40,40,35,35
1. 3 FF stages added in between
1. Now 5 input processing will take 380ns
1. Assuming minimum clock period required is 50ns
1. FF setup is 10ns, assumption.
1. Write Verilog code for Pipelining
1. Assume comb_1, comb_2, comb_3, comb_4 functions available for the 4 stages of the combinational logic.
1. We need to use 2 always blocks.

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